intel: Increase IDC timeout for FPGAs #10249
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serhiy-katsyuba-intel
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lgirdwood
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tmleman
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It may be beneficial to have different timeout values for fast platforms (manufactured silicon) and at least 10 times slower FPGA platforms. Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
With the introduction of LLEXT modules, the time to free a module increased as log_flush() is called as part of module unloading. log_flush() takes 5 ms if at least one line of logs has to be flushed. Let's add these 5 ms to the previous 10 ms IDC timeout to have a default timeout of 15 ms. Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Blocking IDC is used to call comp_free() for a DP component instantiated on a different core than its pipeline. On FPGA, unloading an LLEXT module takes almost 10 ms (for the SRC module, which has a lot of rodata). In addition, log_flush() takes at least 5 ms if there are some logs to flush. However, FPGA seems to have a tendency to have more deferred logs, and log_flush() could take even more time. Let's increase the IDC timeout for FPGA to 50 ms, compared to 15 ms on silicon. Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
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It may be beneficial to have different timeout values for fast platforms (manufactured silicon) and at least 10 times slower FPGA platforms.
Blocking IDC is used to call comp_free() for a DP component instantiated on a different core than its pipeline. With the introduction of LLEXT modules, the time to free a module increased as log_flush() is called as part of module unloading. log_flush() takes 5 ms if at least one line of logs has to be flushed. Let's add these 5 ms to the previous 10 ms IDC timeout to have a default timeout of 15 ms.
On FPGA, unloading an LLEXT module takes almost 10 ms (for the SRC module, which has a lot of rodata). In addition, log_flush() takes at least 5 ms if there are some logs to flush. However, FPGA seems to have a tendency to have more deferred logs, and log_flush() could take even more time. Let's increase the IDC timeout for FPGA to 50 ms, compared to 15 ms on silicon.