intel: Increase IDC timeout for FPGAs

serhiy-katsyuba-intel · abonislawski · commit 46e12d760acb · 2025-09-23T13:15:13.000+02:00
Blocking IDC is used to call comp_free() for a DP component instantiated
on a different core than its pipeline. On FPGA, unloading an LLEXT module
takes almost 10 ms (for the SRC module, which has a lot of rodata).
In addition, log_flush() takes at least 5 ms if there are some logs
to flush. However, FPGA seems to have a tendency to have more deferred
logs, and log_flush() could take even more time. Let's increase the IDC
timeout for FPGA to 50 ms, compared to 15 ms on silicon.

Signed-off-by: Serhiy Katsyuba &lt;serhiy.katsyuba@intel.com&gt;
diff --git a/app/overlays/lnl/fpga_overlay.conf b/app/overlays/lnl/fpga_overlay.conf
@@ -4,3 +4,5 @@ CONFIG_XTENSA_CCOUNT_HZ=40000000
 
 # improves LPSRAM and HPSRAM access time
 CONFIG_SRAM_RETENTION_MODE=n
+
+CONFIG_IDC_TIMEOUT_US=50000
diff --git a/app/overlays/mtl/fpga_overlay.conf b/app/overlays/mtl/fpga_overlay.conf
@@ -4,3 +4,5 @@ CONFIG_XTENSA_CCOUNT_HZ=40000000
 
 # improves LPSRAM and HPSRAM access time
 CONFIG_SRAM_RETENTION_MODE=n
+
+CONFIG_IDC_TIMEOUT_US=50000
diff --git a/app/overlays/nvl/fpga_overlay.conf b/app/overlays/nvl/fpga_overlay.conf
@@ -4,3 +4,5 @@ CONFIG_XTENSA_CCOUNT_HZ=40105000
 
 # limit logs to minimize runtime overhead of logging
 CONFIG_SOF_LOG_LEVEL_ERR=y
+
+CONFIG_IDC_TIMEOUT_US=50000
diff --git a/app/overlays/ptl/fpga_overlay.conf b/app/overlays/ptl/fpga_overlay.conf
@@ -6,3 +6,5 @@ CONFIG_SOF_LOG_LEVEL_ERR=y
 
 # improves LPSRAM and HPSRAM access time
 CONFIG_SRAM_RETENTION_MODE=n
+
+CONFIG_IDC_TIMEOUT_US=50000
diff --git a/app/overlays/wcl/fpga_overlay.conf b/app/overlays/wcl/fpga_overlay.conf
@@ -6,3 +6,5 @@ CONFIG_SOF_LOG_LEVEL_ERR=y
 
 # improves LPSRAM and HPSRAM access time
 CONFIG_SRAM_RETENTION_MODE=n
+
+CONFIG_IDC_TIMEOUT_US=50000
