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intel: Increase IDC timeout for FPGAs #10249

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Merged
abonislawski merged 3 commits into from
Sep 23, 2025
Merged

intel: Increase IDC timeout for FPGAs #10249

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ce5e731
idc: Make IDC timeout value configurable
serhiy-katsyuba-intel Sep 19, 2025
93adac6
idc: Increase default IDC timeout
serhiy-katsyuba-intel Sep 22, 2025
844b21a
intel: Increase IDC timeout for FPGAs
serhiy-katsyuba-intel Sep 19, 2025
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2 changes: 2 additions & 0 deletions app/overlays/lnl/fpga_overlay.conf
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Expand Up @@ -4,3 +4,5 @@ CONFIG_XTENSA_CCOUNT_HZ=40000000

# improves LPSRAM and HPSRAM access time
CONFIG_SRAM_RETENTION_MODE=n

CONFIG_IDC_TIMEOUT_US=50000
2 changes: 2 additions & 0 deletions app/overlays/mtl/fpga_overlay.conf
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Expand Up @@ -4,3 +4,5 @@ CONFIG_XTENSA_CCOUNT_HZ=40000000

# improves LPSRAM and HPSRAM access time
CONFIG_SRAM_RETENTION_MODE=n

CONFIG_IDC_TIMEOUT_US=50000
2 changes: 2 additions & 0 deletions app/overlays/nvl/fpga_overlay.conf
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Expand Up @@ -4,3 +4,5 @@ CONFIG_XTENSA_CCOUNT_HZ=40105000

# limit logs to minimize runtime overhead of logging
CONFIG_SOF_LOG_LEVEL_ERR=y

CONFIG_IDC_TIMEOUT_US=50000
2 changes: 2 additions & 0 deletions app/overlays/ptl/fpga_overlay.conf
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Expand Up @@ -6,3 +6,5 @@ CONFIG_SOF_LOG_LEVEL_ERR=y

# improves LPSRAM and HPSRAM access time
CONFIG_SRAM_RETENTION_MODE=n

CONFIG_IDC_TIMEOUT_US=50000
2 changes: 2 additions & 0 deletions app/overlays/wcl/fpga_overlay.conf
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Expand Up @@ -6,3 +6,5 @@ CONFIG_SOF_LOG_LEVEL_ERR=y

# improves LPSRAM and HPSRAM access time
CONFIG_SRAM_RETENTION_MODE=n

CONFIG_IDC_TIMEOUT_US=50000
3 changes: 0 additions & 3 deletions posix/include/rtos/idc.h
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Expand Up @@ -34,9 +34,6 @@
/** \brief IDC send core power down flag. */
#define IDC_POWER_DOWN 3

/** \brief IDC send timeout in microseconds. */
#define IDC_TIMEOUT 10000

/** \brief IDC task deadline. */
#define IDC_DEADLINE 100

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2 changes: 2 additions & 0 deletions src/Kconfig
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Expand Up @@ -17,6 +17,8 @@ rsource "samples/Kconfig"
rsource "schedule/Kconfig"
rsource "schedule/Kconfig.threads_prio"

rsource "idc/Kconfig"

rsource "ipc/Kconfig"

rsource "math/Kconfig"
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9 changes: 9 additions & 0 deletions src/idc/Kconfig
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@@ -0,0 +1,9 @@
# SPDX-License-Identifier: BSD-3-Clause

config IDC_TIMEOUT_US
int "Timeout for blocking IDC call, microseconds"
default 15000
help
It may be beneficial to have different timeout values
for fast platforms (manufactured silicon) and at least
10 times slower FPGA platforms.
2 changes: 1 addition & 1 deletion src/idc/zephyr_idc.c
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Expand Up @@ -165,7 +165,7 @@ int idc_send_msg(struct idc_msg *msg, uint32_t mode)

switch (mode) {
case IDC_BLOCKING:
ret = k_p4wq_wait(work, K_USEC(IDC_TIMEOUT));
ret = k_p4wq_wait(work, K_USEC(CONFIG_IDC_TIMEOUT_US));
if (!ret)
/* message was sent and executed successfully, get status code */
ret = idc_msg_status_get(msg->core);
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3 changes: 0 additions & 3 deletions zephyr/include/rtos/idc.h
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Expand Up @@ -34,9 +34,6 @@
/** \brief IDC send core power down flag. */
#define IDC_POWER_DOWN 3

/** \brief IDC send timeout in microseconds. */
#define IDC_TIMEOUT 10000

/** \brief IDC task deadline. */
#define IDC_DEADLINE 100

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