Correct speed for SDRAM GPIO pins at higher SDCLK speeds#471
Merged
Conversation
With a SYSCLK at 216MHz, the SDCLK is 108MHz. A GPIO output speed of Speed_50MHz is insufficient for a 108MHz signal. At 108MHz a GPIO output speed of 50MHZ is borderline, and can (does) cause signal integrity issues, especially on a board with marginal silicon. It should be Speed_100MHz or Speed_Very_High (the STM32F7 HAL uses GPIO_SPEED_FREQ_VERY_HIGH for FMC pins).
pat-rogers
changed the title
pat-rogers
changed the title
jklmnn
approved these changes
May 8, 2026
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
With a SYSCLK at 216MHz, the SDCLK is 108MHz. A GPIO output speed of Speed_50MHz is insufficient for a 108MHz signal. 50MHZ is borderline, and can (does) cause signal integrity issues, especially on a board with marginal silicon. It should be Speed_100MHz or Speed_Very_High (the STM32F7 HAL uses GPIO_SPEED_FREQ_VERY_HIGH for FMC pins).
I have observed this change to be necessary at a SYSCLK setting of 216MHz on an F746.