feat: Enhance sv support#522
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Add a Verilog construct dispatcher (_extract_verilog_constructs) that emits Function nodes tagged extra["verilog_kind"] for ANSI/non-ANSI ports, nets/wires, and parameters/localparams, mirroring the existing Solidity construct precedent. Signal-level RTL declarations are now visible in the graph (search, review context, query, impact radius). - parser.py: dispatcher + hook after the Solidity branch; handles list_of_port_declarations (with headerless trailing-port inheritance), input/output/inout_declaration, parameter/local_parameter_declaration, net_declaration, and data_declaration (skipping imports/typedefs) - refactor.py: skip verilog_kind nodes in dead-code detection - sample.sv: wire + localparam, plus a multi-module Top wrapper with wire feedthrough across two submodule instances - test_multilang.py: 9 new TestVerilogParsing assertions Verified in WSL: full suite 1281 passed, ruff + mypy clean. Tier 1 of the SystemVerilog enhancement roadmap (bd crg-7dy). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Tier 2 of the SystemVerilog enhancement roadmap. Adds structural depth on top of the Tier 1 construct dispatcher: - package_declaration -> Class node (registered in _CLASS_TYPES + _get_name), so import utils_pkg::* / arith_pkg::counter_t resolve to real definitions - type_declaration -> Function node, verilog_kind="typedef"; name taken from the direct-child simple_identifier (DFS would wrongly grab the first enum member nested in data_type) - modport_declaration -> Function node per modport_item, verilog_kind="modport", parented to the enclosing interface No refactor.py change needed: the Tier 1 dead-code guard already skips any node carrying verilog_kind. Fixture gains two single-line package defs; TestVerilogParsing gains package/typedef/modport coverage plus a regression guard ensuring enum members never surface as typedef nodes. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Tier 3 of the SystemVerilog enhancement roadmap. Adds signal-level data flow and verification coverage on top of Tiers 1-2. - Named port connections now emit REFERENCES edges from the enclosing module to each referenced local signal, tying instance port maps to the Tier-1 net/port/parameter nodes. Empty maps (.sum()) emit nothing. - covergroup/property/sequence declarations become Function nodes tagged with verilog_kind. Sequence names use the direct-child identifier to avoid the body-signal DFS trap (same fix as typedefs in Tier 2). - interface_instantiation (how the grammar parses instantiations inside generate blocks) is now a call type, so generate-block instantiations get CALLS edges via the existing recursion. All in _extract_verilog_constructs; no changes to the generic class/ function tables. 5 new TestVerilogParsing tests (28 pass); full parser + multilang suite green; ruff and mypy clean. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Adversarial code review of the SystemVerilog support surfaced two silent correctness bugs and a data-model pollution issue; this fixes them. Correctness (parser.py): - Multi-name non-ANSI ports (input a, b; / output c, d;) were dropped entirely -- the handler only walked list_of_port_identifiers, but the grammar emits list_of_variable_identifiers / list_of_variable_port_identifiers for these forms. - Net-typed ANSI ports (output wire [3:0] b) reported the wrong datatype (the stale preceding port type) because the header loop only read a direct data_type child, not net_port_type1; the wrong type also poisoned following headerless ports. - Named-port connections collected bit/part-select index constants (the WIDTH in wr_ptr[WIDTH-1:0]) as data-flow REFERENCES targets. Pollution (signals are modeled as kind=Function + verilog_kind): - changes.py: exclude signal nodes from risk scoring / test-gap detection so a .sv edit no longer floods review output with bogus untested entries. - graph.py get_stats: re-bucket signals under Signal so they do not inflate the user-facing Function count. - graph.py get_nodes_by_size: exclude signals from large-function detection. - refactor.py suggest_refactorings: skip signals in cross-community moves. Tests/fixture: - Add regression tests: multi-name non-ANSI ports, net-typed ANSI datatype, multi-line constructs (disproving the grammar-is-brittle-on-multi-line claim), slice-index exclusion, and dead-code/stats pollution guards. - Correct the misleading multi-line fixture comments. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
…erface_instantiation Extends the SystemVerilog signal-pollution guards to the two remaining material consumers, and corrects a misleading grammar comment. - flows.py detect_entry_points: skip signal-level nodes (ports/nets/params, modeled as Function nodes) so they no longer register as bogus entry-point roots polluting flow tracing. - graph.py get_impact_radius: drop signal nodes from the impacted set. They are leaves reached via CONTAINS/REFERENCES from a touched module, so this removes no real downstream impact but stops every signal of that module from inflating impacted_files and the impact count. - parser.py: investigated the "interface_instantiation is dead code" review claim. It is NOT dead -- the tree-sitter-verilog grammar parses a *parameterized* instantiation inside a generate block (Foo #(.W(W)) inst) as interface_instantiation. Kept the handler; rewrote the comment to state the real reason (the earlier comment's generate-block claim was imprecise). - Add regression tests for the flows + impact-radius guards. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Changes:
Tests: PASS
Linting: PASS