Intel: FPGA: Disable SRAM Retention (FPGA only) #9889
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Disabling SRAM retention improves LPSRAM and HPSRAM access time at the cost of slightly higher power consumption. Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Disabling SRAM retention improves LPSRAM and HPSRAM access time at the cost of slightly higher power consumption. Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Disabling SRAM retention improves LPSRAM and HPSRAM access time at the cost of slightly higher power consumption. On FPGA, with SRAM retention disabled, KPB draining is 2.5 times faster! Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
serhiy-katsyuba-intel
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dbaluta,
kv2019i,
lbetlej,
lgirdwood,
mmaka1 and
plbossart
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tmleman
approved these changes
Mar 11, 2025
lgirdwood
approved these changes
Mar 11, 2025
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Disabling SRAM retention improves LPSRAM and HPSRAM access time at the cost of slightly higher power consumption.
On FPGA, with SRAM retention disabled, KPB draining is 2.5 times faster!