PTL: FPGA: Disable SRAM Retention

Disabling SRAM retention improves LPSRAM and HPSRAM access time at the
cost of slightly higher power consumption.

On FPGA, with SRAM retention disabled, KPB draining is 2.5 times faster!

Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>

Author: serhiy-katsyuba-intel

app/overlays/ptl/fpga_overlay.conf

@@ -3,3 +3,6 @@ CONFIG_DAI_DMIC_HW_IOCLK=19200000
 
 # limit logs to minimize runtime overhead of logging
 CONFIG_SOF_LOG_LEVEL_ERR=y
+
+# improves LPSRAM and HPSRAM access time
+CONFIG_SRAM_RETENTION_MODE=n