xtos: cleanup Kconfig.xtos, remove CONFIG_DMA_GW and other unused options

Kconfig.sof

@@ -1,110 +1,10 @@
 # SPDX-License-Identifier: BSD-3-Clause
 
-config XT_WAITI_DELAY
-	bool
-	default n
-	help
-	  LX6 Xtensa platforms may require additional delay to flush loads
-	  and stores before entering WAITI.
 
 config HOST_PTABLE
 	bool
 	default n
 
-config XT_HAVE_RESET_VECTOR_ROM
-	bool
-	default n
-	help
-	  Select if your platform has the reset vector
-	  in ROM.
-
-config XT_IRQ_MAP
-	bool
-	default n
-
-config DMA_GW
-	bool
-	default n
-
-config MEM_WND
-	bool
-	default n
-
-config INTEL_IOMUX
-	bool
-	default n
-
-config DMA_HW_LLI
-	bool
-	default n
-	help
-	  Hardware linked list is DMA feature, which allows
-	  to automatically reload the next programmed linked list
-	  item from memory without stopping the transfer. Without
-	  it the transfer stops after every lli read and FW needs
-	  to manually setup the next transfer.
-
-	  Any platforms with hardware linked list support
-	  should set this.
-
-config DMA_SUSPEND_DRAIN
-	bool
-	default n
-	help
-	  Some platforms cannot just simple disable DMA
-	  channel during the transfer, because it will
-	  hang the whole DMA controller. Instead we can
-	  suspend the channel and drain the FIFO in order
-	  to stop the channel as soon as possible.
-
-	  Any platforms without the ability to disable
-	  the DMA channel right away should set this.
-
-config DMA_FIFO_PARTITION
-	bool
-	default n
-	help
-	  Some platforms require to manually set DMA
-	  FIFO partitions before starting any transfer.
-
-	  Any platforms without automatic FIFO partitions
-	  should set this.
-
-config XT_INTERRUPT_LEVEL_1
-	bool
-	default n
-	help
-	  Select if the platform supports any interrupts of level 1.
-	  Disabling this option allows for less memory consumption.
-
-config XT_INTERRUPT_LEVEL_2
-	bool
-	default n
-	help
-	  Select if the platform supports any interrupts of level 2.
-	  Disabling this option allows for less memory consumption.
-
-config XT_INTERRUPT_LEVEL_3
-	bool
-	default n
-	help
-	  Select if the platform supports any interrupts of level 3.
-	  Disabling this option allows for less memory consumption.
-
-config XT_INTERRUPT_LEVEL_4
-	bool
-	default n
-	help
-	  Select if the platform supports any interrupts of level 4.
-	  Disabling this option allows for less memory consumption.
-
-config XT_INTERRUPT_LEVEL_5
-	bool
-	default n
-	help
-	  Select if the platform supports any interrupts of level 5.
-	  Disabling this option allows for less memory consumption.
-
 config COMPILER_WORKAROUND_CACHE_ATTR
 	bool
 	default n
@@ -148,6 +48,8 @@ config FAST_GET
 	  counting. Source is src/lib/fast-get.c. The option should be selected
 	  on platforms, where __cold_rodata is supported.
 
+rsource "Kconfig.xtos"
+
 rsource "src/Kconfig"
 
 if ZEPHYR_SOF_MODULE

Kconfig.xtos

@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+# This file contains build options needed to support
+# legacy driver code that still partially rely on XTOS
+# definitions, even when used with Zephyr RTOS.
+#
+# When all platforms have moved over to native Zephyr
+# drivers, this file can be removed
+
+config XT_WAITI_DELAY
+	bool
+	default n
+	help
+	  LX6 Xtensa platforms may require additional delay to flush loads
+	  and stores before entering WAITI.
+
+config XT_HAVE_RESET_VECTOR_ROM
+	bool
+	default n
+	help
+	  Select if your platform has the reset vector
+	  in ROM.
+
+config XT_IRQ_MAP
+	bool
+	default n
+
+config DMA_HW_LLI
+	bool
+	default n
+	help
+	  Hardware linked list is DMA feature, which allows
+	  to automatically reload the next programmed linked list
+	  item from memory without stopping the transfer. Without
+	  it the transfer stops after every lli read and FW needs
+	  to manually setup the next transfer.
+
+	  Any platforms with hardware linked list support
+	  should set this.
+
+config DMA_SUSPEND_DRAIN
+	bool
+	default n
+	help
+	  Some platforms cannot just simple disable DMA
+	  channel during the transfer, because it will
+	  hang the whole DMA controller. Instead we can
+	  suspend the channel and drain the FIFO in order
+	  to stop the channel as soon as possible.
+
+	  Any platforms without the ability to disable
+	  the DMA channel right away should set this.
+
+config DMA_FIFO_PARTITION
+	bool
+	default n
+	help
+	  Some platforms require to manually set DMA
+	  FIFO partitions before starting any transfer.
+
+	  Any platforms without automatic FIFO partitions
+	  should set this.
+
+config XT_INTERRUPT_LEVEL_1
+	bool
+	default n
+	help
+	  Select if the platform supports any interrupts of level 1.
+	  Disabling this option allows for less memory consumption.
+
+config XT_INTERRUPT_LEVEL_2
+	bool
+	default n
+	help
+	  Select if the platform supports any interrupts of level 2.
+	  Disabling this option allows for less memory consumption.
+
+config XT_INTERRUPT_LEVEL_3
+	bool
+	default n
+	help
+	  Select if the platform supports any interrupts of level 3.
+	  Disabling this option allows for less memory consumption.
+
+config XT_INTERRUPT_LEVEL_4
+	bool
+	default n
+	help
+	  Select if the platform supports any interrupts of level 4.
+	  Disabling this option allows for less memory consumption.
+
+config XT_INTERRUPT_LEVEL_5
+	bool
+	default n
+	help
+	  Select if the platform supports any interrupts of level 5.
+	  Disabling this option allows for less memory consumption.

src/include/sof/trace/dma-trace.h

@@ -30,9 +30,6 @@ struct dma_trace_buf {
 struct dma_trace_data {
 	struct dma_sg_config config;
 	struct dma_trace_buf dmatb;
-#if CONFIG_DMA_GW
-	struct dma_sg_config gw_config;
-#endif
 	struct dma_copy dc;
 	struct sof_ipc_dma_trace_posn posn;
 	struct ipc_msg *msg;

src/ipc/dma-copy.c

@@ -23,7 +23,6 @@ SOF_DEFINE_REG_UUID(dma_copy);
 
 DECLARE_TR_CTX(dmacpy_tr, SOF_UUID(dma_copy_uuid), LOG_LEVEL_INFO);
 
-#if !CONFIG_DMA_GW
 static struct dma_sg_elem *sg_get_elem_at(struct dma_sg_config *host_sg,
 	int32_t *offset)
 {
@@ -49,43 +48,11 @@ static struct dma_sg_elem *sg_get_elem_at(struct dma_sg_config *host_sg,
 	tr_err(&dmacpy_tr, "host offset in beyond end of SG buffer");
 	return NULL;
 }
-#endif
 
 /* Copy DSP memory to host memory.
  * Copies DSP memory to host in a single PAGE_SIZE or smaller block. Does not
  * waits/sleeps and can be used in IRQ context.
  */
-#if CONFIG_DMA_GW
-
-int dma_copy_to_host(struct dma_copy *dc, struct dma_sg_config *host_sg,
-		     int32_t host_offset, void *local_ptr, int32_t size)
-{
-	int ret;
-
-	/* tell gateway to copy */
-	ret = dma_copy_legacy(dc->chan, size, DMA_COPY_BLOCKING);
-	if (ret < 0)
-		return ret;
-
-	/* bytes copied */
-	return size;
-}
-
-int dma_copy_to_host_nowait(struct dma_copy *dc, struct dma_sg_config *host_sg,
-			    int32_t host_offset, void *local_ptr, int32_t size)
-{
-	int ret;
-
-	/* tell gateway to copy */
-	ret = dma_copy_legacy(dc->chan, size, 0);
-	if (ret < 0)
-		return ret;
-
-	/* bytes copied */
-	return size;
-}
-
-#else /* CONFIG_DMA_GW */
 
 static int
 dma_copy_to_host_flags(struct dma_copy *dc, struct dma_sg_config *host_sg,
@@ -153,8 +120,6 @@ int dma_copy_to_host_nowait(struct dma_copy *dc, struct dma_sg_config *host_sg,
 				      DMA_COPY_ONE_SHOT);
 }
 
-#endif /* CONFIG_DMA_GW */
-
 int dma_copy_new(struct dma_copy *dc)
 {
 	uint32_t dir, cap, dev;
@@ -169,14 +134,12 @@ int dma_copy_new(struct dma_copy *dc)
 		return -ENODEV;
 	}
 
-#if !CONFIG_DMA_GW
 	/* get DMA channel from DMAC0 */
 	dc->chan = dma_channel_get_legacy(dc->dmac, CONFIG_TRACE_CHANNEL);
 	if (!dc->chan) {
 		tr_err(&dmacpy_tr, "dc->chan is NULL");
 		return -ENODEV;
 	}
-#endif
 
 	return 0;
 }