WORKAROUND: arm64: dts: qcom: enable ethernet on the QPS615 switch for RB3Gen2, Lemans EVK, and Monaco EVK#335
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…switch Enable the 10GbE and 2.5GbE ethernet ports of the QPS615 PCIE switch. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
…15 switch Enable the 10GbE and 2.5GbE ethernet ports of the QPS615 PCIE switch. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
…15 switch Enable the 10GbE and 2.5GbE ethernet ports of the QPS615 PCIE switch. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
shashim-quic
requested changes
Mar 6, 2026
| bus-range = <0x5 0xff>; | ||
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| pci@0,0 { | ||
| eth0_pci: pci@0,0 { |
| }; | ||
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| pci@0,1 { | ||
| eth1_pci: pci@0,1 { |
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| #include <dt-bindings/interrupt-controller/irq.h> | ||
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| ð0_pci { |
There was a problem hiding this comment.
I think you use node name directly and avoid adding labelling
| }; | ||
| }; | ||
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| ð1_pci { |
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| #include <dt-bindings/interrupt-controller/irq.h> | ||
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| ð0_pci { |
| }; | ||
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| pci@0,1 { | ||
| eth1_pci: pci@0,1 { |
| }; | ||
| }; | ||
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| ð0_pci { |
| }; | ||
| }; | ||
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| ð1_pci { |
| bus-range = <0x5 0xff>; | ||
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| pci@0,0 { | ||
| eth0_pci: pci@0,0 { |
| }; | ||
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| pci@0,1 { | ||
| eth1_pci: pci@0,1 { |
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This PR enables the 10GbE (AQR113C) and 2.5GbE (QCA8081) Ethernet ports of the QPS615 PCIe switch on three Qualcomm platforms: RB3Gen2, IQ 9075 EVK, and IQ 8275 EVK.
Each platform follows the same pattern:
eth0_pci:andeth1_pci:DT node labels to the existingpci@0,0andpci@0,1nodes insidepcie@3,0in the board's base DTS/DTSO*-qps615.dtsifile containing all QPS615-specific configuration (regulators, PHY reset GPIOs, WoL interrupt pinctrl, and IOMMU groups)