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[RFCT] clk and removal #95

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29 changes: 12 additions & 17 deletions hw/ip/spatz/src/vregfile.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -77,31 +77,26 @@
end: gen_row_decoder

// Column decoder. Create a clock for each SCM column
logic [WordWidth/8-1:0] col_clk;
for (genvar b = 0; b < WordWidth/8; b++) begin: gen_col_decoder
tc_clk_gating i_wbe_cg (
.clk_i (clk ),
.en_i (wbe_i[b] ),
.test_en_i(testmode_i),
.clk_o (col_clk[b])
);
end: gen_col_decoder
logic [NrWords-1:0][WordWidth/8-1:0] col_clk;
for (genvar row = 0; row < NrWords; row++) begin: gen_row
for (genvar b = 0; b < WordWidth/8; b++) begin: gen_col_decoder

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GitHub Actions / lint-sv 

[verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

Raw Output:
message:"Use spaces, not tabs. [Style: tabs] [no-tabs]" location:{path:"hw/ip/spatz/src/vregfile.sv" range:{start:{line:82 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
tc_clk_gating i_wbe_cg (

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GitHub Actions / lint-sv 

[verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

Raw Output:
message:"Use spaces, not tabs. [Style: tabs] [no-tabs]" location:{path:"hw/ip/spatz/src/vregfile.sv" range:{start:{line:83 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.clk_i (row_clk[row]),

Check warning on line 84 in hw/ip/spatz/src/vregfile.sv

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GitHub Actions / lint-sv 

[verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

Raw Output:
message:"Use spaces, not tabs. [Style: tabs] [no-tabs]" location:{path:"hw/ip/spatz/src/vregfile.sv" range:{start:{line:84 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.en_i (wbe_i[b] ),

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GitHub Actions / lint-sv 

[verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

Raw Output:
message:"Use spaces, not tabs. [Style: tabs] [no-tabs]" location:{path:"hw/ip/spatz/src/vregfile.sv" range:{start:{line:85 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.test_en_i(testmode_i),

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GitHub Actions / lint-sv 

[verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

Raw Output:
message:"Use spaces, not tabs. [Style: tabs] [no-tabs]" location:{path:"hw/ip/spatz/src/vregfile.sv" range:{start:{line:86 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.clk_o (col_clk[row][b])

Check warning on line 87 in hw/ip/spatz/src/vregfile.sv

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GitHub Actions / lint-sv 

[verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

Raw Output:
message:"Use spaces, not tabs. [Style: tabs] [no-tabs]" location:{path:"hw/ip/spatz/src/vregfile.sv" range:{start:{line:87 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
);

Check warning on line 88 in hw/ip/spatz/src/vregfile.sv

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GitHub Actions / lint-sv 

[verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

Raw Output:
message:"Use spaces, not tabs. [Style: tabs] [no-tabs]" location:{path:"hw/ip/spatz/src/vregfile.sv" range:{start:{line:88 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
end: gen_col_decoder

Check warning on line 89 in hw/ip/spatz/src/vregfile.sv

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GitHub Actions / lint-sv 

[verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

Raw Output:
message:"Use spaces, not tabs. [Style: tabs] [no-tabs]" location:{path:"hw/ip/spatz/src/vregfile.sv" range:{start:{line:89 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
end: gen_row

// Select which destination bytes to write into

// Store new data to memory
/* verilator lint_off NOLATCH */
for (genvar vreg = 0; vreg < NrWords; vreg++) begin: gen_write_mem
for (genvar b = 0; b < WordWidth/8; b++) begin: gen_word
logic clk_latch;
tc_clk_and2 i_clk_and (
.clk0_i(row_clk[vreg]),
.clk1_i(col_clk[b] ),
.clk_o (clk_latch )
);

always_latch begin
if (clk_latch)
if (col_clk[vreg][b])
mem[vreg][b] <= wdata_q[b*8 +: 8];
end
end: gen_word
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