[RFCT] clk and removal

[rgiunti]

Summary

This PR refactors the latch clock generation in vregfile.sv by replacing the per-cell tc_clk_and2 between row and column clocks with a cascaded tc_clk_gating structure. The functional behavior is unchanged.

Motivation

While the current implementation works, AND-ing two clock signals is generally considered a pattern that requires extra care in the backend flow (possible narrow glitches, some lint/CDC tools may give high-severity warnings).

Changes

Column-level tc_clk_gating is now driven by row_clk[row] as its input clock. This produces a per-cell gated clock col_clk[row][b] directly, with no AND of clocks.

Notes

The proposed changes have been simulated with a local CI based on Questasim and synthesized with Synopsys DC in GF22.