[chip,dv] Define a virtual "chip_ral" core#30140
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This gets defined in the cores for chip environments. The advantage is that these cores can now depend on the environments of IPs, which won't generate their own RAL definitions (because the chip-level environment has done it already). Note that this is different from the existing skip_ral_gen flag. As far as I can tell, there's no way to set a flag for just the cores that get pulled in as a dependencie. So skip_ral_gen will let you turn everything off, but I don't think you can turn off just the RAL for the blocks. To set the "chip_level" flag, it has to be set to true in the core file that gets invoked by fusesoc (I think). This is chip_sim.core. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
Splitting it up like this will allow us to integrate a block-level testbench, whose register model is generated in the chip-level RAL file. We need to split that out of chip_env.core to avoid a circular dependency (because the chip environment depends on the block-level environment, which depends on the register model). Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
This is supplied by a top-level chip-level register model. Defining it like this means that a block-level environment can depend on lowrisc:dv:chip_ral if the chip_level config parameter is set, which will ensure it appears in the EDA file list *after* the register model upon which it depends. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
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This PR is a draft because it depends on both #29727 and #29730. Once they are merged, only the last commit remains, which has the following commit message.