[rstmgr,dv] Reset Manager DV ported to mocha by KolosKoblasz-Semify · Pull Request #506 · lowRISC/mocha

KolosKoblasz-Semify · 2026-04-29T14:16:41Z

This PR ports Reset Manager Controller DV code from Opentitan to Mocha.

This PR will address: #433 --- Close #433

Project specific tests:

dvsim hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson -i all --cov

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	3.000s	136.016us	50	50	100.00 %
V1	csr_hw_reset	rstmgr_csr_hw_reset	2.000s	111.025us	5	5	100.00 %
V1	csr_rw	rstmgr_csr_rw	2.000s	48.825us	20	20	100.00 %
V1	csr_bit_bash	rstmgr_csr_bit_bash	4.000s	399.817us	5	5	100.00 %
V1	csr_aliasing	rstmgr_csr_aliasing	2.000s	82.431us	5	5	100.00 %
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	2.000s	81.480us	20	20	100.00 %
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	2.000s	48.825us	20	20	100.00 %
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_aliasing	2.000s	82.431us	5	5	100.00 %
V1		TOTAL			105	105	100.00 %
V2	reset_stretcher	rstmgr_por_stretcher	2.000s	169.324us	50	50	100.00 %
V2	sw_rst	rstmgr_sw_rst	3.000s	73.373us	50	50	100.00 %
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	2.000s	110.607us	50	50	100.00 %
V2	reset_info	rstmgr_reset	8.000s	1218.362us	50	50	100.00 %
V2	cpu_info	rstmgr_reset	8.000s	1218.362us	50	50	100.00 %
V2	alert_info	rstmgr_reset	8.000s	1218.362us	50	50	100.00 %
V2	reset_info_capture	rstmgr_reset	8.000s	1218.362us	50	50	100.00 %
V2	stress_all	rstmgr_stress_all	41.000s	8037.084us	50	50	100.00 %
V2	alert_test	rstmgr_alert_test	2.000s	56.500us	50	50	100.00 %
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.000s	233.976us	20	20	100.00 %
V2	tl_d_illegal_access	rstmgr_tl_errors	3.000s	233.976us	20	20	100.00 %
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	2.000s	111.025us	5	5	100.00 %
V2	tl_d_outstanding_access	rstmgr_csr_rw	2.000s	48.825us	20	20	100.00 %
V2	tl_d_outstanding_access	rstmgr_csr_aliasing	2.000s	82.431us	5	5	100.00 %
V2	tl_d_outstanding_access	rstmgr_same_csr_outstanding	2.000s	62.854us	20	20	100.00 %
V2	tl_d_partial_access	rstmgr_csr_hw_reset	2.000s	111.025us	5	5	100.00 %
V2	tl_d_partial_access	rstmgr_csr_rw	2.000s	48.825us	20	20	100.00 %
V2	tl_d_partial_access	rstmgr_csr_aliasing	2.000s	82.431us	5	5	100.00 %
V2	tl_d_partial_access	rstmgr_same_csr_outstanding	2.000s	62.854us	20	20	100.00 %
V2		TOTAL			370	370	100.00 %
V2S	tl_intg_err	rstmgr_sec_cm	11.000s	4930.623us	5	5	100.00 %
V2S	tl_intg_err	rstmgr_tl_intg_err	3.000s	753.951us	20	20	100.00 %
V2S	prim_count_check	rstmgr_sec_cm	11.000s	4930.623us	5	5	100.00 %
V2S	prim_fsm_check	rstmgr_sec_cm	11.000s	4930.623us	5	5	100.00 %
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.000s	753.951us	20	20	100.00 %
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	2.000s	110.430us	50	50	100.00 %
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	4.000s	444.930us	23	50	46.00 %
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	2.000s	70.811us	50	50	100.00 %
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	11.000s	4930.623us	5	5	100.00 %
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	2.000s	48.825us	20	20	100.00 %
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	2.000s	48.825us	20	20	100.00 %
V2S		TOTAL			168	195	86.15 %
		TOTAL			593	620	95.65 %

Coverage Results

Coverage Dashboard

TOTAL	BLOCK	LINE/STATEMENT	BRANCH	TOGGLE	FSM	ASSERTION	FUNCTIONAL
94.18 %	94.78 %	94.67 %	90.47 %	96.99 %	72.11 %	96.01 %	97.96 %

Failure Buckets

UVM_FATAL (rstmgr_leaf_rst_cnsty_vseq.sv:159) [rstmgr_leaf_rst_cnsty_vseq] Timeout waiting for alert fatal_cnsty_fault has 27 failures:
- Test rstmgr_leaf_rst_cnsty has 27 failures.
  - 1.rstmgr_leaf_rst_cnsty.45788128805664214418475274298876099271975220649024862745597390570666361824047
    Line 93, in log /home/kkoblasz/projects/mocha/scratch/kk_rst_mgr_dv/rstmgr.sim.xcelium/1.rstmgr_leaf_rst_cnsty/latest/run.log
```
  UVM_INFO @  77241116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.rstmgr_leaf_rst_cnsty.43535571888821152156200193949083009951604505169671122206112137140095695086956
    Line 93, in log /home/kkoblasz/projects/mocha/scratch/kk_rst_mgr_dv/rstmgr.sim.xcelium/2.rstmgr_leaf_rst_cnsty/latest/run.log
```
  UVM_INFO @ 102318303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 25 more failures.
    
    [ legend ]: [S: scheduled, Q: queued, R: running, P: passed, F: failed, K: killed, T: total]
    00:01:14 [ build ]: [S: 000, Q: 000, R: 000, P: 002, F: 000, K: 000, T: 002] 100%
    00:02:35 [ run ]: [S: 000, Q: 000, R: 000, P: 593, F: 027, K: 000, T: 620] 100%
    00:03:05 [ cov_merge ]: [S: 000, Q: 000, R: 000, P: 001, F: 000, K: 000, T: 001] 100%
    00:03:12 [ cov_report ]: [S: 000, Q: 000, R: 000, P: 001, F: 000, K: 000, T: 001] 100%

Top level tests:
dvsim hw/top_chip/dv/mocha_sim_cfgs.hjson --select-cfgs rstmgr -i smoke --cov

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	2.000s	80.330us	1	1	100.00 %
V1	csr_hw_reset	rstmgr_csr_hw_reset	1.000s	77.999us	1	1	100.00 %
V1	csr_rw	rstmgr_csr_rw	1.000s	55.891us	1	1	100.00 %
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	1.000s	55.891us	1	1	100.00 %
V1		TOTAL			3	3	100.00 %
V2	tl_d_outstanding_access	rstmgr_csr_rw	1.000s	55.891us	1	1	100.00 %
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	1.000s	77.999us	1	1	100.00 %
V2	tl_d_partial_access	rstmgr_csr_rw	1.000s	55.891us	1	1	100.00 %
V2	tl_d_partial_access	rstmgr_csr_hw_reset	1.000s	77.999us	1	1	100.00 %
V2		TOTAL			2	2	100.00 %
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	1.000s	55.891us	1	1	100.00 %
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	1.000s	55.891us	1	1	100.00 %
V2S		TOTAL			1	1	100.00 %
		TOTAL			3	3	100.00 %

Coverage Results

Coverage Dashboard

TOTAL	BLOCK	LINE/STATEMENT	BRANCH	TOGGLE	FSM	ASSERTION	FUNCTIONAL
62.87 %	85.97 %	85.15 %	74.39 %	91.59 %	17.69 %	90.02 %	31.38 %

TOP_MOCHA_BATCH_SIM Simulation Results (Summary)

Tuesday May 12 2026 17:45:09 UTC

Github Revision: `cf832c4`

Branch: kk_rst_mgr_dv

Name	Passing	Total	Pass Rate	Coverage
RSTMGR	3	3	100.00 %	62.87 %

      [   legend    ]: [S: scheduled, Q: queued, R: running, P: passed, F: failed, K: killed, T: total]

00:00:07 [ build ]: [S: 0, Q: 0, R: 0, P: 2, F: 0, K: 0, T: 2] 100%
00:00:08 [ run ]: [S: 0, Q: 0, R: 0, P: 3, F: 0, K: 0, T: 3] 100%
00:00:12 [ cov_merge ]: [S: 0, Q: 0, R: 0, P: 1, F: 0, K: 0, T: 1] 100%
00:00:16 [ cov_report ]: [S: 0, Q: 0, R: 0, P: 1, F: 0, K: 0, T: 1] 100%

martin-velay · 2026-04-29T14:36:45Z

      - files_rtl
      - files_dv
-    default_tool: vcs
+    default_tool: xcelium


This is the source of your issue with the src file being not generated. The .src file is your file list generated from FuseSoc. I know that confusing, I went into this trap earlier too.
The VCS backend generates a .scr file, which is an identical format to a more standard .f format. We are only running FuseSoc up to the point it generates the filelist file (.scr in this case).

marnovandermaas · 2026-05-05T13:41:22Z

-    // Wait till rst_lc_n is inactive for non-aon.
-    `DV_WAIT(cfg.rstmgr_vif.resets_o.rst_lc_n[1])
+    // Wait till rst_por_aon_n is inactive for non-aon.
+    `DV_WAIT(cfg.rstmgr_vif.resets_o.rst_por_aon_n[1])


I think this should be the same reset as the one fed into the reset manager block in the top which is rst_por_io_n

In rstmgr.sv line 351 constant zero is assigned to it:

The assignment happens here: rstmgr.sv#L340

Probably makes sense to switch rst_*lc* with rst_por_io_n everywhere (and Marno agrees as well).

Okay, but then it is DomainAonSel right?

rst_lc_n[1] -> rst_por_io_n[1] so this is going to be Domain0Sel?

Yes, DomainAonSel is 0, Domain0Sel is 1.

marnovandermaas

Some comments from my end.

marnovandermaas · 2026-05-08T12:48:37Z

+-  `CASCADED_ASSERTS(CascadeLcToLc, rst_lc_src_n[rstmgr_pkg::Domain0Sel],
+-                    resets_o.rst_lc_n[rstmgr_pkg::Domain0Sel], SysCycles, clk_main_i)
+-
+-  // Controlled by rst_sys_src_n.


There are a few resets controlled by SYS SRC in Mocha, such as rst_{main,io,spi_device,spi_host,i2c}_n

It would be good to investigate whether we should have cascade asserts for those.

marnovandermaas · 2026-05-08T12:49:51Z

+ else:
+     assert 0, "No preferred clock available"
+
+-preferred_rst_n = f"rst_lc_{preferred_domain}_n"


Can't we just update the preferred domain? This also fixes the power on reset preference below.

* open titan specific paths changed to mocha specific ones in the template files * 0001_Fix_Paths_And_Tools.patch file created with the changes Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

* The patched config and template config files added to the source code Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

* 0002 patches fix the auto generated reset manager's dv files to be run Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

* These modifications will enable to run block level simulations on rstmgr while using correct reset signals and domains in the UVM tb. Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

* rstmgr's smoketest added to top level simulation list Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

* changes in hw/vendor/patches/lowrisc_ip/i2c/0002-Fix-Widths.patch file got implemented in upstream repo, making this patch redundant. * this commit removes the patch file Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

* Upstream repo now contains the patch file, therfore hw/vendor/patches/lowrisc_ip/prim_xilinx/0001_Mem_Init_String.patch is deleted Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7e53929271cf69fce17966be5b665ba91df17694 * [alert,dv] Don't return too early from a ping (Rupert Swarbrick) * [dv] Rationalise dv_base_driver reset tracking (Rupert Swarbrick) * [dv] Restructure the way jtag_dmi_reg_frontdoor is given dmi/dtmcs (Rupert Swarbrick) * [aes/dv] Add RAL type override to allow separating GCM and non-GCM DV (Pirmin Vogel) * [hw/otbn] Add new HPC gadgets (Hakim Filali) * [prim/rtl] Improve prim_fifo_async_simple for rv_dm and lc_ctrl (Neil Webb) * [clkmgr/cdc] Deglitch on shadow register error alerts (Neil Webb) * [prim/rtl] Explicitly assign values to FSM states in prim_sync_reqack (Neil Webb) * [rstmgr, DV] Fixed the message and ID body inside (Kinza Qamar) * [i2c,hw] Correct assign/compare widths (Elliot Baptist) * [dv] Pass is_active from cip_base_env_cfg to alert and TL agents (Rupert Swarbrick) * [dv] Stop jtag_dmi_monitor depending on jtag_agent_cfg (Rupert Swarbrick) * [dv] Beta-reduce slightly silly templating in fpv_csr.sv.tpl (Rupert Swarbrick) * [dv] Fix REGWEN_PATH in fpv_csr.sv.tpl (Rupert Swarbrick) * [top/templates] Indentation and whitespaces fixes (Florian Glaser) * [topgen] Automatically generate port map for toplevels (Florian Glaser) * [clkmgr,dv] Fix invalid type in clkmgr_regwen_vseq (Rupert Swarbrick) * [tl,dv] Make TL assertions cause simulation failure when they fail (Rupert Swarbrick) * [topgen,sw] Fix operations between different enum types, part II (Luís Marques) * [rv_plic,rtl] Move the onehot0 checks to rv_plic_gateway (Rupert Swarbrick) * [rv_plic,doc] Add some careful documentation to rv_plic_gateway.sv (Rupert Swarbrick) * [rv_plic,rtl] Simplify code for ia update in the gateway (Rupert Swarbrick) * [rv_plic,rtl] Simplify ip_o rule in rv_plic_gateway (Rupert Swarbrick) * [rv_plic,fpv] Add an assertion about relationship between ia and ip (Rupert Swarbrick) * [I2C, dv] Removed unused argument (Kinza Qamar) * [tl,dv] Clear the stop flag at the end, not the start, of body() (Rupert Swarbrick) * [I2C, dv] Simplified i2c_device_response seq's drive_read_byte() (Kinza Qamar) * [i2c/rtl] Change VAL register input to synced SCL/SDA (Neil Webb) * [I2C, dv] Removed the unused i2c_dv_if (Kinza Qamar) * [dv] Simplify key sideload driver (Rupert Swarbrick) * [dv] Allow a cfg to be passed directly to dv_base_agent (Rupert Swarbrick) * [hw,prim] Add new prim_inv (Hakim Filali) * [prim] Add prim_flop_x module to wrap different prim_flop variants (Pirmin Vogel) * [dv] Remove csr_base_addr argument from dv_base_env_cfg::initialize (Rupert Swarbrick) * [dv] Add "Monitor" to if_mode_e (Rupert Swarbrick) * [hw] gpiodpi: fix backwards log message (Alice Ziuziakowska) * [pwrmgr,dv] Remove do-nothing $assertoff (Rupert Swarbrick) Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

* As result of previous patches to template files new dv files are generated for rstmgr. Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

KolosKoblasz-Semify requested review from marnovandermaas and martin-velay April 29, 2026 14:16

martin-velay changed the title ~~Reset Manager DV ported to mocha~~ [rstmgr,dv] Reset Manager DV ported to mocha Apr 29, 2026

martin-velay reviewed Apr 29, 2026

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KolosKoblasz-Semify force-pushed the kk_rst_mgr_dv branch 6 times, most recently from d7f29db to 7d337b2 Compare May 5, 2026 11:14

marnovandermaas reviewed May 5, 2026

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KolosKoblasz-Semify force-pushed the kk_rst_mgr_dv branch 3 times, most recently from a5c3e8f to 3d667b7 Compare May 8, 2026 09:33

marnovandermaas reviewed May 8, 2026

View reviewed changes

KolosKoblasz-Semify added 2 commits May 11, 2026 10:46

[rstmgr_dv, vendoring] Reset Manager paths patched

095a98c

* open titan specific paths changed to mocha specific ones in the template files * 0001_Fix_Paths_And_Tools.patch file created with the changes Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

[rstmgr, vendoring] Patched Configfiles commited

82a8fe4

* The patched config and template config files added to the source code Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

KolosKoblasz-Semify force-pushed the kk_rst_mgr_dv branch from 3d667b7 to 8b0d9b8 Compare May 11, 2026 11:05

KinzaQamar reviewed May 12, 2026

View reviewed changes

Comment thread hw/top_chip/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv

KolosKoblasz-Semify added 7 commits May 12, 2026 18:32

[rstmgr_dv, vendoring] Template file patches added

76ac4ee

* 0002 patches fix the auto generated reset manager's dv files to be run Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

[rstmgr, vendoring] Fixed template files commited

1a5b599

* These modifications will enable to run block level simulations on rstmgr while using correct reset signals and domains in the UVM tb. Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

[rstmgr, dv] rstmgr added to top level dv

a756ec0

* rstmgr's smoketest added to top level simulation list Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

[i2c, vendoring] Not needed .patch files removed

6de1fae

* changes in hw/vendor/patches/lowrisc_ip/i2c/0002-Fix-Widths.patch file got implemented in upstream repo, making this patch redundant. * this commit removes the patch file Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

[prim_xilinx, vendoring] Not needed .patch files removed

7c92f05

* Upstream repo now contains the patch file, therfore hw/vendor/patches/lowrisc_ip/prim_xilinx/0001_Mem_Init_String.patch is deleted Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

[rstmgr_dv, autogen] Autogenerated code added

cf832c4

* As result of previous patches to template files new dv files are generated for rstmgr. Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>

KolosKoblasz-Semify force-pushed the kk_rst_mgr_dv branch from 8b0d9b8 to cf832c4 Compare May 12, 2026 17:47

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Test Results

Coverage Results

Failure Buckets

Test Results

Coverage Results

TOP_MOCHA_BATCH_SIM Simulation Results (Summary)

Tuesday May 12 2026 17:45:09 UTC

Github Revision: cf832c4

Branch: kk_rst_mgr_dv

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KolosKoblasz-Semify commented Apr 29, 2026 •

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Github Revision: `cf832c4`