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KolosKoblasz-SemifyKolosKoblasz-Semify
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[rstmgr_dv, autogeneration] rstmgr files autogenerated from templates
 * Since templates files were chnaged to enable running block level simulations the rstmgr files had to be regenerated and commited. Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>
1 parent c383541 commit 7d337b2

7 files changed

Lines changed: 21 additions & 33 deletions

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‎hw/top_chip/ip_autogen/rstmgr/data/rstmgr_testplan.hjson‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3,12 +3,12 @@
33
// SPDX-License-Identifier: Apache-2.0
44
{
55
name: "rstmgr"
6-
import_testplans: ["hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
7-
"hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
8-
"hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
9-
"hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
10-
"hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson",
11-
"hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
6+
import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
7+
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson",
8+
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
9+
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
10+
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson",
11+
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
1212
"rstmgr_sec_cm_testplan.hjson"]
1313

1414
testpoints: [

‎hw/top_chip/ip_autogen/rstmgr/dv/env/rstmgr_if.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,5 +65,5 @@ interface rstmgr_if (
6565
always_comb cpu_info_en = `PATH_TO_DUT.reg2hw.cpu_info_ctrl.en.q;
6666

6767
bit rst_ni_inactive;
68-
always_comb rst_ni_inactive = resets_o.rst_lc_io_n[rstmgr_pkg::Domain0Sel];
68+
always_comb rst_ni_inactive = resets_o.rst_por_aon_n[rstmgr_pkg::Domain0Sel];
6969
endinterface

‎hw/top_chip/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -115,8 +115,8 @@ class rstmgr_reset_vseq extends rstmgr_base_vseq;
115115
expected_cpu_enable = 0;
116116

117117
cfg.clk_rst_vif.wait_clks(8);
118-
// Wait till rst_lc_n is inactive for non-aon.
119-
`DV_WAIT(cfg.rstmgr_vif.resets_o.rst_lc_n[1])
118+
// Wait till rst_por_aon_n is inactive for non-aon.
119+
`DV_WAIT(cfg.rstmgr_vif.resets_o.rst_por_aon_n[1])
120120

121121
check_reset_info(get_reset_code(start_reset, 0), {reset_name[start_reset], " reset"});
122122
check_alert_info_after_reset(expected_alert_dump, expected_alert_enable);
@@ -172,7 +172,7 @@ class rstmgr_reset_vseq extends rstmgr_base_vseq;
172172
reset_done();
173173

174174
cfg.io_clk_rst_vif.wait_clks(8);
175-
wait(cfg.rstmgr_vif.resets_o.rst_lc_n[1]);
175+
wait(cfg.rstmgr_vif.resets_o.rst_por_aon_n[1]);
176176
check_reset_info(expected_reset_info_code);
177177
check_alert_info_after_reset(.alert_dump(expected_alert_dump),
178178
.enable(expected_alert_enable));

‎hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@
2121
testplan: "{self_dir}/data/rstmgr_cnsty_chk_testplan.hjson"
2222

2323
// Import additional common sim cfg files.
24-
import_cfgs: ["{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson"]
24+
import_cfgs: ["{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson"]
2525

2626

2727
// Specific exclusion files.

‎hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
tb: tb
1313

1414
// Simulator used to sign off this block
15-
tool: vcs
15+
tool: xcelium
1616

1717
// Fusesoc core file used for building the file list.
1818
fusesoc_core: lowrisc:mocha_dv:rstmgr_sim:0.1
@@ -25,16 +25,16 @@
2525

2626
// Import additional common sim cfg files.
2727
import_cfgs: [// Project wide common sim cfg file
28-
"{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
28+
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson",
2929
// Common CIP test lists
30-
"{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
31-
"{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
32-
"{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
33-
"{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
30+
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
31+
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
32+
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson",
33+
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
3434
// Just run the stress_all sequence, and don't inject random
3535
// resets since we may get overlapping resets due to sequences
3636
// that inject them.
37-
"{proj_root}/hw/dv/tools/dvsim/tests/stress_all_test.hjson"
37+
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_all_test.hjson"
3838
]
3939

4040
// Specific exclusion files.

‎hw/top_chip/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv‎

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -158,18 +158,6 @@ interface rstmgr_cascading_sva_if (
158158
`CASCADED_ASSERTS(CascadeEffAonToRstPorMain, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
159159
resets_o.rst_por_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_main_i)
160160

161-
// Controlled by rst_lc_src_n.
162-
`CASCADED_ASSERTS(CascadeLcToLcAon, rst_lc_src_n[rstmgr_pkg::DomainAonSel],
163-
resets_o.rst_lc_aon_n[rstmgr_pkg::DomainAonSel], SysCycles, clk_aon_i)
164-
`CASCADED_ASSERTS(CascadeLcToLc, rst_lc_src_n[rstmgr_pkg::Domain0Sel],
165-
resets_o.rst_lc_n[rstmgr_pkg::Domain0Sel], SysCycles, clk_main_i)
166-
167-
// Controlled by rst_sys_src_n.
168-
`CASCADED_ASSERTS(CascadeSysToSys, rst_sys_src_n[rstmgr_pkg::Domain0Sel],
169-
resets_o.rst_sys_n[rstmgr_pkg::Domain0Sel], PeriCycles, clk_main_i)
170-
`CASCADED_ASSERTS(CascadeLcToLcShadowed, rst_lc_src_n[rstmgr_pkg::Domain0Sel],
171-
resets_o.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel], SysCycles, clk_main_i)
172-
173161
`undef FALL_ASSERT
174162
`undef RISE_ASSERTS
175163
`undef CASCADED_ASSERTS

‎hw/top_chip/ip_autogen/rstmgr/dv/tb.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ module tb;
4040

4141
tl_if tl_if (
4242
.clk,
43-
.rst_n(rstmgr_if.resets_o.rst_lc_io_n[rstmgr_pkg::Domain0Sel])
43+
.rst_n(rstmgr_if.resets_o.rst_por_aon_n[rstmgr_pkg::Domain0Sel])
4444
);
4545

4646
rstmgr_if rstmgr_if (
@@ -63,7 +63,7 @@ module tb;
6363
// This is consistent with rstmgr being the only source of resets.
6464
rstmgr dut (
6565
.clk_i (clk),
66-
.rst_ni (rstmgr_if.resets_o.rst_lc_io_n[rstmgr_pkg::Domain0Sel]),
66+
.rst_ni (rstmgr_if.resets_o.rst_por_aon_n[rstmgr_pkg::Domain0Sel]),
6767
.clk_aon_i (clk_aon),
6868
.clk_io_i (clk_io),
6969
.clk_main_i (clk_main),
@@ -118,7 +118,7 @@ module tb;
118118
// This may help any code that depends on clk_rst_vif.rst_n in the infrastructure: they won't
119119
// be able to change but at least the reset value will be true to the environment.
120120
clk_rst_if.drive_rst_n = 1'b0;
121-
force clk_rst_if.rst_n = rstmgr_if.resets_o.rst_lc_io_n[rstmgr_pkg::Domain0Sel];
121+
force clk_rst_if.rst_n = rstmgr_if.resets_o.rst_por_aon_n[rstmgr_pkg::Domain0Sel];
122122
end
123123

124124
endmodule

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