Fix: 4 deferred L2 swimlane correctness bugs in a2a3 from #916 review#936
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Bundled fixes for issues CodeRabbit flagged during hw-native-sys#916 review and agreed to defer to a follow-up. All four are tight per-site fixes without behavior change beyond the affected corner case. 1. scheduler_cold_path::init — phase pool count: pass `aicpu_thread_num_` (not `sched_thread_num_`) when `orch_to_sched_=true`. When orch merges into sched, phase records flow through aicpu-thread-indexed pools; the old code under-allocated when `aicpu_thread_num_ > sched_thread_num_`, silently dropping the tail. Matches the existing branch in `scheduler_dispatch.cpp:489` (dump_tensor_init). 2. scheduler_cold_path::init — reset cached level on disabled runs: if `is_l2_swimlane_enabled()` is false this launch, also clear `l2_swimlane_level_` to DISABLED. Without this, a stale value from a prior enabled launch on the same scheduler instance leaks into the `>= SCHED_PHASES` gates in scheduler_dispatch, which then writes into a non-initialized phase pool. 3. onboard/aicore/kernel.cpp::KERNEL_ENTRY — always publish the rotation slot (nullptr when disabled this launch). `[[block_local]]` storage persists across launches on the same loaded binary, so without an explicit nullptr publication the stale slot from a prior enabled launch survives, and `get_l2_swimlane_aicore_rotation()` returns a freed device pointer. Mirrors the sim wrapper's always-publish pattern. 4. l2_swimlane_collector.h::resolve_entry — validate `entry.kind` before branching. Previously any out-of-range value silently fell into the AicoreTask branch and read a wrong-typed pool. The new guard logs and returns nullopt for unknown kinds. Test coverage: existing `test_l2_swimlane` / `test_l2_swimlane_mixed` sim tests pass unchanged. Bug 1 trigger requires `PTO2_ORCH_TO_SCHED=1` + `SCHED_PHASES` level + phase-pool-count assertion, which the current swimlane test infra doesn't model; bugs 2/3 trigger requires enabled→disabled launch cycling within one process. These test gaps are deferred to a separate test-infra PR rather than expanded inline to keep this fix focused.
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Mechanical backport of two of the four bugs landed for a2a3 in #936. The a5 file has the identical code shape at the same call site (scheduler_cold_path.cpp:854-860), so the patch is the same shape: 1. l2_swimlane_aicpu_init_phase phase pool count: pass `aicpu_thread_num_` (not `sched_thread_num_`) when `orch_to_sched_=true`. Mirrors the existing precedent in `src/a5/.../scheduler_dispatch.cpp:494` (`dump_tensor_init`). Without this, `PTO2_ORCH_TO_SCHED=1` + `SCHED_PHASES` level + `aicpu_thread_num_ > sched_thread_num_` under-allocates phase pools and silently drops the tail records. 2. Reset `l2_swimlane_level_` to DISABLED when `is_l2_swimlane_enabled() == false` this launch. Without this, a prior enabled launch's cached level leaks into the `>= SCHED_PHASES` gates in scheduler_dispatch (a5 scheduler_dispatch.cpp:517 reads the same field), writing into an uninitialized phase pool on the disabled-this-launch run. a2a3 Bugs 3 and 4 do NOT apply to a5: - Bug 3 (AICore rotation slot stale leak): a5 uses a fixed per-core ring (`L2SwimlaneAicoreRing` with dual_issue_slots), not a rotated buffer pool, and `src/a5/platform/onboard/aicore/kernel.cpp:113-118` already publishes `set_aicore_l2_swimlane_ring(nullptr)` in the disabled branch. - Bug 4 (resolve_entry invalid kind): a5 `L2SwimlaneBufferKind` is a binary `is_phase` flag (only AicpuTask/AicpuPhase, no AicoreTask), so the wrong-typed-pool fall-through doesn't exist in the same form. Test plan: - Build all four variants (a5 + a2a3, onboard + sim) — clean - pytest tests/st/a5/.../dummy_task --platform a5sim — passes - pre-commit clean Co-authored-by: Chao Wang <26245345+ChaoWao@users.noreply.github.com>
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Summary
Bundled fixes for four issues CodeRabbit flagged during #916 review and agreed to defer. Scope: a2a3 only. Bugs 1 and 2 also exist verbatim in
src/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_cold_path.cpp(a5 has the same code shape); a follow-up will bulk-port the same edits across all a5 sites — keeping a5 out of this PR avoids interleaving an a2a3 bugfix with a cross-arch sweep.src/a2a3/.../scheduler_cold_path.cppl2_swimlane_aicpu_init_phaseusessched_thread_num_instead oforch_to_sched_ ? aicpu_thread_num_ : sched_thread_num_PTO2_ORCH_TO_SCHED=1+SCHED_PHASESlevel +aicpu_thread_num_ > sched_thread_num_; under-allocates phase pools and silently drops the tail recordssrc/a2a3/.../scheduler_cold_path.cppl2_swimlane_level_not reset whenis_l2_swimlane_enabled() == false(no else branch);sched_ctx_.deinit()doesn't clear it either>= SCHED_PHASESgates inscheduler_dispatch.cpp:516/627/710/777/804/827, writing into a non-initialized phase pool on the disabled-this-launch runsrc/a2a3/platform/onboard/aicore/kernel.cpp[[block_local]]storage persists across launchesenabled(valid table) → enabled(NULL table)orenabled → disabledleavesget_l2_swimlane_aicore_rotation()returning the prior launch's freed pointer. Current AICore call sites are themselves flag-gated on this-launchl2_swimlane_enabled, so the disabled-launch path is unreachable through the executors; the unconditional reset is defensive against future call sites without that gate.src/a2a3/.../l2_swimlane_collector.hresolve_entryfalls into the AicoreTask branch for any out-of-rangeentry.kindBug 1's fix mirrors the existing branch in
scheduler_dispatch.cpp:489(dump_tensor_init). Bug 3 mirrors the publish-nullptr branch insim/aicore/kernel.cpp:122-130(sim keys only on table pointer; onboard additionally AND-gates onPROFILING_FLAG_L2_SWIMLANE).Architecture scope
src/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_cold_path.cpp:854-860; will land via a follow-up bulk port that also handles other a5/a2a3 swimlane divergence. Bug 3 doesn't apply to a5 (src/a5/platform/onboard/aicore/kernel.cpp:113-118already publishesset_aicore_l2_swimlane_ring(nullptr)in the disabled branch). Bug 4 is milder on a5 (binaryis_phasecheck, no AicoreTask branch to fall into).Testing
test_l2_swimlaneandtest_l2_swimlane_mixedsim tests pass unchanged.PTO2_ORCH_TO_SCHED=1+SCHED_PHASES+ a phase-pool-count assertion.Test plan
pytest test_l2_swimlane.py --platform a2a3sim --enable-l2-swimlanepytest test_l2_swimlane_mixed.py --platform a2a3sim --enable-l2-swimlanepre-commit runclean on all touched files