Fix: port a2a3 L2 swimlane Bugs 1+2 to a5 scheduler_cold_path#940
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Mechanical backport of two of the four bugs landed for a2a3 in hw-native-sys#936. The a5 file has the identical code shape at the same call site (scheduler_cold_path.cpp:854-860), so the patch is the same shape: 1. l2_swimlane_aicpu_init_phase phase pool count: pass `aicpu_thread_num_` (not `sched_thread_num_`) when `orch_to_sched_=true`. Mirrors the existing precedent in `src/a5/.../scheduler_dispatch.cpp:494` (`dump_tensor_init`). Without this, `PTO2_ORCH_TO_SCHED=1` + `SCHED_PHASES` level + `aicpu_thread_num_ > sched_thread_num_` under-allocates phase pools and silently drops the tail records. 2. Reset `l2_swimlane_level_` to DISABLED when `is_l2_swimlane_enabled() == false` this launch. Without this, a prior enabled launch's cached level leaks into the `>= SCHED_PHASES` gates in scheduler_dispatch (a5 scheduler_dispatch.cpp:517 reads the same field), writing into an uninitialized phase pool on the disabled-this-launch run. a2a3 Bugs 3 and 4 do NOT apply to a5: - Bug 3 (AICore rotation slot stale leak): a5 uses a fixed per-core ring (`L2SwimlaneAicoreRing` with dual_issue_slots), not a rotated buffer pool, and `src/a5/platform/onboard/aicore/kernel.cpp:113-118` already publishes `set_aicore_l2_swimlane_ring(nullptr)` in the disabled branch. - Bug 4 (resolve_entry invalid kind): a5 `L2SwimlaneBufferKind` is a binary `is_phase` flag (only AicpuTask/AicpuPhase, no AicoreTask), so the wrong-typed-pool fall-through doesn't exist in the same form. Test plan: - Build all four variants (a5 + a2a3, onboard + sim) — clean - pytest tests/st/a5/.../dummy_task --platform a5sim — passes - pre-commit clean
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Code Review
This pull request updates SchedulerContext::init to reset l2_swimlane_level_ to DISABLED when swimlanes are disabled, preventing state leakage from previous launches. It also dynamically determines the number of phase threads based on the orch_to_sched_ flag. The reviewer suggests using int32_t instead of int for phase_threads to ensure type consistency and avoid potential compiler warnings.
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Summary
Mechanical backport of two of the four L2 swimlane bugs landed for a2a3 in #936. The a5 file has the identical code shape at the same call site (
scheduler_cold_path.cpp:854-860), so the patch is the same shape (+11 / -2 lines).l2_swimlane_aicpu_init_phaseusessched_thread_num_instead oforch_to_sched_ ? aicpu_thread_num_ : sched_thread_num_PTO2_ORCH_TO_SCHED=1+SCHED_PHASESlevel +aicpu_thread_num_ > sched_thread_num_; under-allocates phase pools and silently drops tail recordsl2_swimlane_level_not reset whenis_l2_swimlane_enabled() == false(no else branch)>= SCHED_PHASESgates inscheduler_dispatch.cpp(a5 site atscheduler_dispatch.cpp:517reads the same field), writing into an uninitialized phase pool on the disabled-this-launch runBug 1's fix mirrors the existing precedent in
src/a5/.../scheduler_dispatch.cpp:494(dump_tensor_initalready uses theorch_to_sched_ternary).Why only 2 of the 4 bugs
The a5 swimlane subsystem architecturally diverges from a2a3 — Bugs 3 and 4 don't apply in the same form:
L2SwimlaneAicoreRingwithdual_issue_slots), not a rotated buffer pool.src/a5/platform/onboard/aicore/kernel.cpp:113-118already publishesset_aicore_l2_swimlane_ring(nullptr)in the disabled branch.resolve_entryinvalid kind): a5L2SwimlaneBufferKindis a binaryis_phaseflag (onlyAicpuTask/AicpuPhase, noAicoreTask), so the wrong-typed-pool fall-through doesn't exist in the same form.Test plan
pytest tests/st/a5/tensormap_and_ringbuffer/dummy_task --platform a5simpassespre-commit runcleanDependency
Independent of #936 (a2a3) — touches a different arch. Can land in either order.