Riscv sifive u74-mc / starfive jh7110#234
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hugomeiland wants to merge 4 commits into
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Add description and detection string for this cpu:
{EESSI/2025.06} user@starfive:/cvmfs/software.eessi.io/versions/2025.06/init$ ./eessi_archdetect.sh -d cpupath
2026-05-21 12:11:26 [DEBUG] cpupath: Override variable set as ''
2026-05-21 12:11:26 [DEBUG] cpupath: Host CPU architecture identified as 'riscv64'
2026-05-21 12:11:26 [DEBUG] cpupath: CPU vendor of host system: '0x489'
2026-05-21 12:11:26 [DEBUG] cpupath: Known CPU vendors: 0x489 0x710 0x710
2026-05-21 12:11:26 [DEBUG] cpupath: CPU flags of host system: 'rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb'
2026-05-21 12:11:26 [INFO] cpupath: best match for host CPU: riscv64/generic
riscv64/generic
{EESSI/2025.06} user@starfive:/cvmfs/software.eessi.io/versions/2025.06/init$ cat /proc/cpuinfo
processor : 0
hart : 1
isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb
mmu : sv39
uarch : sifive,u74-mc
mvendorid : 0x489
marchid : 0x8000000000000007
mimpid : 0x4210427
hart isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb
processor : 1
hart : 2
isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb
mmu : sv39
uarch : sifive,u74-mc
mvendorid : 0x489
marchid : 0x8000000000000007
mimpid : 0x4210427
hart isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb
processor : 2
hart : 3
isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb
mmu : sv39
uarch : sifive,u74-mc
mvendorid : 0x489
marchid : 0x8000000000000007
mimpid : 0x4210427
hart isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb
processor : 3
hart : 4
isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb
mmu : sv39
uarch : sifive,u74-mc
mvendorid : 0x489
marchid : 0x8000000000000007
mimpid : 0x4210427
hart isa : rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd_zba_zbb