Use debug mode with word

docs/debug_mode.md

@@ -0,0 +1,193 @@
+# Vortex Debug Mode with GDB
+
+This guide explains how to debug Vortex programs using GDB and OpenOCD with the RISC-V debug interface.
+
+## Prerequisites
+
+Before running the debugger, ensure you have the following dependencies installed:
+
+- **OpenOCD**: Open On-Chip Debugger for JTAG communication
+- **RISC-V GDB**: RISC-V cross-debugger (part of RISC-V toolchain, e.g., `riscv64-unknown-elf-gdb`)
+- **Build tools**: Make and C++ compiler (g++)
+
+## Building the Simulator and Kernel Files
+
+### Building the Simulator
+
+The simulator must be built with `XLEN=64` to support 64-bit RISC-V binaries (including double-precision floating point):
+
+```bash
+cd /vortex
+cd build/sim/simx
+make clean
+make XLEN=64
+```
+
+This builds the simulator with:
+- **XLEN=64**: 64-bit integer registers
+- **EXT_D enabled**: Double-precision floating point support (FLEN=64)
+- **RISC-V Debug Module**: Full debug interface support
+
+### Building the Kernel Library
+
+The kernel library (`libvortex.a`) must be built with the same `XLEN` value as the simulator. For 64-bit support:
+
+```bash
+cd /vortex/build/kernel
+make clean
+make XLEN=64
+```
+
+This builds the kernel library that provides system calls, startup code, and runtime support for Vortex programs.
+
+### Building Test Binaries
+
+All test binaries must also be built with `XLEN=64` to match the simulator and kernel library:
+
+```bash
+# Build a specific test (e.g., fibonacci)
+cd /vortex/build/tests/kernel/fibonacci
+make clean
+make XLEN=64
+
+# Or build all kernel tests
+cd /vortex/build/tests/kernel
+for dir in */; do
+    cd "$dir"
+    make clean
+    make XLEN=64
+    cd ..
+done
+```
+
+**Important:** The `XLEN` value must be consistent across:
+- Simulator (`build/sim/simx`)
+- Kernel library (`build/kernel`)
+- All test binaries (`build/tests/kernel/*`)
+
+Mismatched `XLEN` values will cause linker errors or runtime failures.
+
+## Quick Start: Debugging Fibonacci
+
+### Step 1: Start Simulator in Debug Mode
+
+```bash
+cd /vortex
+./build/sim/simx/simx -d build/tests/kernel/fibonacci/fibonacci.bin
+```
+
+For verbose debug logging (optional, shows detailed debug module operations):
+```bash
+./build/sim/simx/simx -d -V 9824 build/tests/kernel/fibonacci/fibonacci.bin
+```
+
+The simulator starts halted, waiting for a debugger connection.
+
+### Step 2: Start OpenOCD
+
+```bash
+openocd -f vortex.cfg
+```
+
+**Note:** `vortex.cfg` uses port 9824. If using default port 9823, either:
+- Start simulator with `-p 9824`, or
+- Update `vortex.cfg` to use port 9823
+
+### Step 3: Connect GDB
+
+```bash
+riscv64-unknown-elf-gdb build/tests/kernel/fibonacci/fibonacci.elf
+```
+
+In GDB:
+```
+(gdb) target remote localhost:3333
+(gdb) monitor reset halt
+(gdb) set $pc = 0x80000000
+(gdb) break main
+(gdb) continue
+```
+
+## Common GDB Commands
+
+```bash
+# Breakpoints
+(gdb) break main
+(gdb) break fibonacci
+(gdb) break main.cpp:16
+
+# Execution control
+(gdb) continue          # Continue execution
+(gdb) step             # Step into function
+(gdb) next             # Step over function
+(gdb) stepi            # Step one instruction
+(gdb) nexti            # Next instruction
+
+# Inspection
+(gdb) print variable
+(gdb) info registers
+(gdb) x/10i $pc        # Disassemble 10 instructions
+(gdb) x/s 0x80005740   # Print string at address
+```
+
+## Command-Line Options
+
+```bash
+./build/sim/simx/simx [options] <program.bin>
+
+Options:
+  -d              Enable debug mode
+  -p <port>       Remote bitbang port (default: 9823)
+  -V              Enable verbose debug module logging (shows detailed debug operations)
+  -c <cores>      Number of cores
+  -w <warps>      Number of warps per core
+  -t <threads>    Number of threads per warp
+```
+
+**Note:** The `-V` flag enables verbose logging from the debug module, which shows detailed information about register accesses, memory operations, and debug commands. This is useful for debugging the debugger itself, but can produce a lot of output. Use it when you need to see what the debug module is doing internally.
+
+## Key Addresses (Fibonacci Binary)
+
+| Address | Function/Data |
+|---------|---------------|
+| 0x80000000 | `_start` (entry point) |
+| 0x80000094 | `fibonacci()` |
+| 0x80000114 | `main()` |
+| 0x800001ac | `init_regs()` (final PC) |
+| 0x80005740 | `"fibonacci(%d) = %d\n"` |
+| 0x80005754 | `"Passed!\n"` |
+| 0x8000575c | `"Failed! value=%d, expected=%d\n"` |
+
+## Troubleshooting
+
+**OpenOCD can't connect:**
+- Verify simulator is running with `-d` flag
+- Check port numbers match (default 9823, config uses 9824)
+- Check simulator output for "Remote bitbang server ready"
+
+## Example Session
+
+```bash
+# Terminal 1 (add -V for verbose debug logging)
+./build/sim/simx/simx -d -p 9824 build/tests/kernel/fibonacci/fibonacci.bin
+
+# Terminal 2
+openocd -f vortex.cfg
+
+# Terminal 3
+riscv64-unknown-elf-gdb
+(gdb) target remote localhost:3333
+(gdb) stepi
+(gdb) b *0x80000094
+(gdb) continue
+(gdb) i r
+(gdb) continue
+Continuing.
+Program Stopped
+```
+
+## Additional Resources
+
+- [RISC-V Debug Specification](https://github.com/riscv/riscv-debug-spec)
+- [OpenOCD Documentation](http://openocd.org/doc/html/index.html)
+- [GDB User Manual](https://sourceware.org/gdb/current/onlinedocs/gdb/)

hw/rtl/tcu/VX_tcu_fedp_bhf.sv

@@ -47,12 +47,16 @@ module VX_tcu_fedp_bhf #(
 
     wire [TCK-1:0][15:0] a_row16;
     wire [TCK-1:0][15:0] b_col16;
+    wire [N-1:0][18:0]   a_row_tf32;
+    wire [N-1:0][18:0]   b_col_tf32;
 
     for (genvar i = 0; i < N; i++) begin : g_unpack
         assign a_row16[2*i]   = a_row[i][15:0];
         assign a_row16[2*i+1] = a_row[i][31:16];
         assign b_col16[2*i]   = b_col[i][15:0];
         assign b_col16[2*i+1] = b_col[i][31:16];
+        assign a_row_tf32[i]  = a_row[i][18:0];
+        assign b_col_tf32[i]  = b_col[i][18:0];
     end
 
     // Transprecision Multiply
@@ -75,6 +79,7 @@ module VX_tcu_fedp_bhf #(
     for (genvar i = 0; i < TCK; i++) begin : g_prod
         wire [32:0] mult_result_fp16;
         wire [32:0] mult_result_bf16;
+        wire [32:0] mult_result_tf32;
 
         // FP16 multiplication
         VX_tcu_bhf_fmul #(
@@ -118,11 +123,37 @@ module VX_tcu_fedp_bhf #(
             `UNUSED_PIN(fflags)
         );
 
+        if ((i % 2) == 0) begin : g_tf32_even
+            localparam int TF32_IDX = i / 2;
+            VX_tcu_bhf_fmul #(
+                .IN_EXPW (8),
+                .IN_SIGW (10+1),
+                .OUT_EXPW(8),
+                .OUT_SIGW(24),
+                .IN_REC  (0), // TF32 stored in IEEE-like format
+                .OUT_REC (1), // output in recoded format
+                .MUL_LATENCY (FMUL_LATENCY),
+                .RND_LATENCY (FRND_LATENCY)
+            ) tf32_mul (
+                .clk    (clk),
+                .reset  (reset),
+                .enable (enable),
+                .frm    (frm),
+                .a      (a_row_tf32[TF32_IDX]),
+                .b      (b_col_tf32[TF32_IDX]),
+                .y      (mult_result_tf32),
+                `UNUSED_PIN(fflags)
+            );
+        end else begin : g_tf32_odd
+            assign mult_result_tf32 = '0;
+        end
+
         logic [32:0] mult_result_mux;
         always_comb begin
             case(fmt_s_delayed)
                 3'd1: mult_result_mux = mult_result_fp16;
                 3'd2: mult_result_mux = mult_result_bf16;
+                3'd3: mult_result_mux = mult_result_tf32;
                 default: mult_result_mux = 'x;
             endcase
         end

hw/rtl/tcu/VX_tcu_pkg.sv

@@ -29,6 +29,7 @@ package VX_tcu_pkg;
     localparam TCU_FP32_ID = 0;
     localparam TCU_FP16_ID = 1;
     localparam TCU_BF16_ID = 2;
+    localparam TCU_TF32_ID = 3;
     localparam TCU_I32_ID  = 8;
     localparam TCU_I8_ID   = 9;
     localparam TCU_U8_ID   = 10;
@@ -82,18 +83,23 @@ package VX_tcu_pkg;
 
     // Tracing info
 `ifdef SIMULATION
-    task trace_fmt(input int level, input [3:0] fmt);
+    function automatic string fmt_string(input [3:0] fmt);
         case (fmt)
-            TCU_FP32_ID: `TRACE(level, ("fp32"))
-            TCU_FP16_ID: `TRACE(level, ("fp16"))
-            TCU_BF16_ID: `TRACE(level, ("bf16"))
-            TCU_I32_ID:  `TRACE(level, ("i32"))
-            TCU_I8_ID:   `TRACE(level, ("i8"))
-            TCU_U8_ID:   `TRACE(level, ("u8"))
-            TCU_I4_ID:   `TRACE(level, ("i4"))
-            TCU_U4_ID:   `TRACE(level, ("u4"))
-            default:     `TRACE(level, ("?"))
+            TCU_FP32_ID: fmt_string = "fp32";
+            TCU_FP16_ID: fmt_string = "fp16";
+            TCU_BF16_ID: fmt_string = "bf16";
+            TCU_TF32_ID: fmt_string = "tf32";
+            TCU_I32_ID:  fmt_string = "i32";
+            TCU_I8_ID:   fmt_string = "i8";
+            TCU_U8_ID:   fmt_string = "u8";
+            TCU_I4_ID:   fmt_string = "i4";
+            TCU_U4_ID:   fmt_string = "u4";
+            default:     fmt_string = "unknown";
         endcase
+    endfunction
+
+    task trace_fmt(input int level, input [3:0] fmt);
+        `TRACE(level, (fmt_string(fmt)))
     endtask
 
     task trace_ex_op(input int level,

sim/common/tensor_cfg.h

@@ -43,6 +43,13 @@ struct bf16 {
   static constexpr const char* name = "bf16";
 };
 
+struct tf32 {
+  using dtype = uint32_t;
+  static constexpr uint32_t id = 3;
+  static constexpr uint32_t bits = 32;
+  static constexpr const char* name = "tf32";
+};
+
 struct int32 {
   using dtype = int32_t;
   static constexpr uint32_t id = 8;
@@ -83,12 +90,13 @@ inline const char* fmt_string(uint32_t fmt) {
   case fp32::id:  return fp32::name;
   case fp16::id:  return fp16::name;
   case bf16::id:  return bf16::name;
+  case tf32::id:  return tf32::name;
   case int32::id: return int32::name;
   case int8::id:  return int8::name;
   case uint8::id: return uint8::name;
   case int4::id:  return int4::name;
   case uint4::id: return uint4::name;
-  default:        return "";
+  default:        return "unknown";
   }
 }
 

sim/simx/Makefile

@@ -26,6 +26,7 @@ SRCS += $(SRC_DIR)/decode.cpp $(SRC_DIR)/opc_unit.cpp $(SRC_DIR)/dispatcher.cpp
 SRCS += $(SRC_DIR)/execute.cpp $(SRC_DIR)/func_unit.cpp
 SRCS += $(SRC_DIR)/cache_sim.cpp $(SRC_DIR)/mem_sim.cpp $(SRC_DIR)/local_mem.cpp $(SRC_DIR)/mem_coalescer.cpp
 SRCS += $(SRC_DIR)/dcrs.cpp $(SRC_DIR)/types.cpp
+SRCS += $(SRC_DIR)/jtag_dtm.cpp $(SRC_DIR)/debug_module.cpp $(SRC_DIR)/remote_bitbang.cpp
 
 # Add V extension sources
 ifneq ($(findstring -DEXT_V_ENABLE, $(CONFIGS)),)

sim/simx/cluster.h

@@ -69,6 +69,10 @@ class Cluster : public SimObject<Cluster> {
 
   PerfStats perf_stats() const;
 
+  const std::vector<Socket::Ptr>& sockets() const {
+    return sockets_;
+  }
+
 private:
   uint32_t                    cluster_id_;
   ProcessorImpl*              processor_;

sim/simx/core.h

@@ -159,6 +159,10 @@ class Core : public SimObject<Core> {
     return emulator_.dcache_write(data, addr, size);
   }
 
+  Emulator& emulator() {
+    return emulator_;
+  }
+
 #ifdef EXT_TCU_ENABLE
   TensorUnit::Ptr& tensor_unit() {
     return tensor_unit_;