Analog to Digital Converter Control Interface

This document specifies the OTP MACRO hardware IP functionality.

OpenTitan Rv Core Ibex IP block

OpenTitan Flash Ctrl IP block

The mailbox IP block in the OpenTitan Integrated design implements a request-response channel that the host System-on-Chip (SoC) may use to request security ser

Keccak Message Authentication Code (KMAC) and Secure Hashing Algorithm 3 (SHA3)

ROM controller (rom_ctrl) is the connection between the chip and its ROM

Entropy Distribution Network (EDN) interfaces to the CSRNG IP module

System Reset Controller (sysrst_ctrl) that provides programmable hardware-level responses to trusted IOs and basic board-level reset sequencing capabilities

RISC-V Debug System wrapper functionality

Entropy Source: interface to an external physical random noise generator

OpenTitan UART IP - Full duplex serial communication peripheral with programmable baud rate, RX/TX buffers, and interrupt support

OpenTitan Otp Ctrl IP block

USB 2.0 Full-Speed Device

Life Cycle Controller

Cryptographically Secure Random Number Generator (CSRNG)

I2C controller

OpenTitan Prim Generic IP block

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OpenTitan Prim Xilinx Ultrascale IP block