A Datapath design which able to execute store operation as memory instruction, substraction and or operations as arithmetic instruction by Logisim. Additional explanations in readme.
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Updated
Jun 23, 2021
A Datapath design which able to execute store operation as memory instruction, substraction and or operations as arithmetic instruction by Logisim. Additional explanations in readme.
VHDL project implementing a single-cycle MIPS processor, including ALU, control units, register file, memories, and full instruction execution, verified via ModelSim simulation (Digital Circuit Design, UNIWA).
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