FuzzyNSGA-II-Algorithm (Fuzzy adaptive optimisation method)

⚡ A collection of Digital Logic Design (DLD) lab work and projects 🔌. Includes circuit designs, truth tables, simulations, and practical implementations. Covers core concepts of logic gates, combinational & sequential circuits, and hands-on problem-solving in digital systems.

VHDL project for a single-bit memory cell. Demonstrates digital logic design.

Play with digital logic in the browser: drag gates and inputs, wire them up, and watch signals flow— a modern rebuild.

VHDL projects for combinational and sequential logic design on FPGA.

acadamic course in campus il about building a modern computer from basic logic gates such as "nand" to a general computer architecture that is designed execute any program such as "Tetris". and also building assambler

This is a repository exclusively created for providing open source verilog codes for various processor microarchitectures and various programming language based codes for research purpose

⏱️ A step-by-step Logisim Evolution guide for building a digital stopwatch – COS10004 Assignment 1 (2024).

🔧 Welcome to the Digital Systems and Microprocessors Repository! 📚✨ Immerse yourself in a meticulously curated knowledge reservoir on Digital Systems and Microprocessors. 🌐💡 Explore the intricacies of digital circuitry, processor architectures, and system design. 🚀💻 Master the art of efficient digital computing in this dynamic space! 👨‍💻🌐

University of Antioquia. Digital Electronics. Sequential circuits using flip flops

A glimpse into the inner workings of flip flops and their applications

Implementation of integrated circuits

Digital Design laboratory project exploring shift registers, sliders, and information transfer using D flip-flops and 74LS194 ICs, with interactive simulation in NI Multisim (Logic Design, UNIWA).

porject from designing with VHDL course. Includes, FSM (finite state machine), next state logic,seven-segment-display-decode, full adder, flip flops, D_flip-flops, ripple carry adder, full adder, half adder, delay propagation

A digital logic circuit that monitors and displays water tank levels using combinational logic, sequential circuits with D flip-flops (4013), and hierarchical gate design for real-time percentage-based level indication.

VHDL project for implementing sequential circuits (latches, flip-flops, registers, counters, shift registers) with testbench-based verification in ModelSim (Digital Circuit Design, UNIWA).

Repository containing digital circuit projects developed for the INF01058 course at UFRGS.

Digital Design laboratory project exploring sequential logic circuits, including latches and flip-flops (RS, D, JK, T, Master-Slave), with interactive NI Multisim simulations and detailed documentation (Logic Design, UNIWA).

HDLBit-Pratice. https://hdlbits.01xz.net/wiki/Main_Page

This repository focuses on designing and simulating logical circuits using Verilog HDL (Hardware Description Language) with the Icarus Verilog simulator.