kpb: KPB fixes #9885
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kpb: KPB fixes #9885
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period_copy_start is a timestamp measured in wall-clock cycles. It should be a 64-bit unsigned value. Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Given: x = a + b - (a - c), reduce to: x = c + b Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
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Replace the verbose 'if-else' with simpler code using the MIN() macro. Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
The kpb->host_sink is NULL after a reset or unbind. The host could send a reset IPC while the draining task is still running, which results in a crash. Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
The draining task could run for quite a long time (e.g., a few seconds). It is implemented as an EDF scheduler task. While working, it blocks other EDF scheduler tasks: the IPC processing task and the mtrace logging task. The fix replaces the while loop in the draining task with a return SOF_TASK_STATE_RESCHEDULE, so other EDF scheduler tasks can have CPU time. Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
The previous drain interval calculation ignored the actual DSP load by LL and only worked for light LL loads (high DSP clock). The drain interval was not appropriate for slow FPGA, where LL takes half of the DSP time. This update introduces code that dynamically readjusts the drain interval and does not depend on LL load (works on low clock, FPGA). Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
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kv2019i
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Looks good! And great commit messages @serhiy-katsyuba-intel , very easy to follow.
lyakh
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lgirdwood
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Mainly two fixes:
Avoid long seizure of EDF scheduler thread.
The draining task could run for quite a long time (e.g., a few seconds). It is implemented as an EDF scheduler task. While working, it blocks other EDF scheduler tasks: the IPC processing task and the mtrace logging task. The fix replaces the while loop in the draining task with a return SOF_TASK_STATE_RESCHEDULE, so other EDF scheduler tasks can have CPU time.
Fix drain interval calculation
The previous drain interval calculation ignored the actual DSP load by LL and only worked for light LL loads (high DSP clock). The drain interval was not appropriate for slow FPGA, where LL takes half of the DSP time. This update introduces code that dynamically readjusts the drain interval and does not depend on LL load (works on low clock, FPGA).