Topology2: Add sof-ptl-rt712-l3-rt1320-l3 support #9704
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@macchian ping |
not ready to validate, to be added multilane configuration into bios. stay tuned. |
These necessary pipeline configurations apply only when deep buffer speaker feature is enabled. Following commit f35420 (Revert "topology2: Update deep buffer and BT offload for ptl rt722 topology") Signed-off-by: Mac Chiang <mac.chiang@intel.com>
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@macchian is validation now done ? |
yes, it's verified. |
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test results missing in CI - rerun. |
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SOFCI TEST |
The topology supports rt712_vb multi-function codec and rt1320 on SoundWire link 3 and shareing the sdw3-clock, sdw3-data[0], sdw3-data[1] data lanes and without/with PCH_DMIC support. Signed-off-by: Mac Chiang <mac.chiang@intel.com>
kv2019i
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The BT PCM handling is a bit confused now (see inline), but given this matches with the merged kernel PRs, let's go and merge this one.
| SDW_JACK_OUT_STREAM=Playback-SimpleJack,SDW_JACK_IN_STREAM=Capture-SimpleJack,\ | ||
| PREPROCESS_PLUGINS=nhlt,NHLT_BIN=nhlt-sof-ptl-rt712-l3-rt1320-l3-4ch.bin,DMIC0_ENHANCED_CAPTURE=true,\ | ||
| EFX_DMIC0_TDFB_PARAMS=line4_pass,EFX_DMIC0_DRC_PARAMS=dmic_default,\ | ||
| BT_PCM_ID=20,BT_ID=10,BT_PCM_NAME=Bluetooth,ADD_BT=true,\ |
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@macchian This is a bit confusing BT offload is only enabled for the 4ch dmic variant.
FYI @bardliao this is also now a bit unconsistent when only some devices supported by kernel set the BT offload quirk bit. E.g. this sof-ptl-rt712-l3-rt1320-l3-4ch will only work for Chromebooks with current kernel.
Not sure how to best tackle this, but we need some systematic approach to naming these tplgs that can be used both in Chromebook sand desktop Linux. Maybe just enable BT always if there's any configuration that needs it (like in this case). FYI @ujfalusi @ranj063
@bardliao The kernel part is already in so I guess we need to proceed with
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For reference, the kernel part was merged as thesofproject/linux#5258 |
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The topology supports rt712_vb multi-function codec and rt1320 on SoundWire link 3 and shareing the sdw3-clock, sdw3-data[0] and sdw3-data[1] data lanes.