Skip to content
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 0 additions & 4 deletions src/platform/ace30/include/platform/lib/clk.h
Original file line number Diff line number Diff line change
Expand Up @@ -26,12 +26,8 @@

#define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX

#define SSP_DEFAULT_IDX 1

#define NUM_CPU_FREQ 3

#define NUM_SSP_FREQ 3

#define PRIMARY_CORE_BASE_CPS_USAGE 20000
#define SECONDARY_CORE_BASE_CPS_USAGE 10000

Expand Down
16 changes: 1 addition & 15 deletions src/platform/intel/ace/include/ace/lib/clk.h
Original file line number Diff line number Diff line change
Expand Up @@ -20,30 +20,16 @@

#include <ace/version.h>
#include <sof/lib/cpu.h>
#include <sof/lib/io.h>
#include <sof/lib/memory.h>
#include <stdint.h>

struct sof;

/** \brief Core(s) settings, up to CONFIG_CORE_COUNT */
#define CLK_CPU(x) (x)

/** \brief SSP clock r-t settings are after the core(s) settings */
#define CLK_SSP CONFIG_CORE_COUNT

/* SSP clock run-time data is the last one, so total number is ssp idx +1 */

/** \brief Total number of clocks */
#define NUM_CLOCKS (CLK_SSP + 1)
#define NUM_CLOCKS CONFIG_CORE_COUNT

extern const struct freq_table *cpu_freq;

void platform_clock_init(struct sof *sof);

void platform_clock_on_waiti(void);
void platform_clock_on_wakeup(void);

#endif /* __ACE_LIB_CLK_H__ */

#else
Expand Down
3 changes: 2 additions & 1 deletion src/platform/intel/ace/platform.c
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,8 @@ int platform_init(struct sof *sof)
scheduler_init_edf();

/* init low latency timer domain and scheduler. Any failure is fatal */
sof->platform_timer_domain = zephyr_domain_init(PLATFORM_DEFAULT_CLOCK);
/* clk is ignored on Zephyr so pass 0 */
sof->platform_timer_domain = zephyr_domain_init(0);
ret = scheduler_init_ll(sof->platform_timer_domain);
if (ret < 0)
return ret;
Expand Down
4 changes: 0 additions & 4 deletions src/platform/lunarlake/include/platform/lib/clk.h
Original file line number Diff line number Diff line change
Expand Up @@ -24,12 +24,8 @@

#define CPU_DEFAULT_IDX CPU_IPLL_FREQ_IDX

#define SSP_DEFAULT_IDX 1

#define NUM_CPU_FREQ 2

#define NUM_SSP_FREQ 3

#define PRIMARY_CORE_BASE_CPS_USAGE 20000
#define SECONDARY_CORE_BASE_CPS_USAGE 10000

Expand Down
4 changes: 0 additions & 4 deletions src/platform/meteorlake/include/platform/lib/clk.h
Original file line number Diff line number Diff line change
Expand Up @@ -24,12 +24,8 @@

#define CPU_DEFAULT_IDX CPU_IPLL_FREQ_IDX

#define SSP_DEFAULT_IDX 1

#define NUM_CPU_FREQ 2

#define NUM_SSP_FREQ 3

#define PRIMARY_CORE_BASE_CPS_USAGE 20000
#define SECONDARY_CORE_BASE_CPS_USAGE 10000

Expand Down
8 changes: 8 additions & 0 deletions zephyr/lib/clk.c
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,14 @@ void platform_clock_init(struct sof *sof)

sof->clocks = platform_clocks_info;

/*
* plafforms using this clk.c implementation must
* declare the CPU clocks first, and there must be at least
* one clock per core. If this model doesn't fit, platform
* needs a custom platform_clock_init.
*/
BUILD_ASSERT(NUM_CLOCKS >= CONFIG_CORE_COUNT, "Invalid NUM_CLOCKS");

for (i = 0; i < CONFIG_CORE_COUNT; i++) {
sof->clocks[i] = (struct clock_info) {
.freqs_num = NUM_CPU_FREQ,
Expand Down
Loading