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2 changes: 2 additions & 0 deletions src/ipc/ipc-common.c
Original file line number Diff line number Diff line change
Expand Up @@ -55,9 +55,11 @@ int ipc_process_on_core(uint32_t core, bool blocking)
return -EACCES;
}

#if CONFIG_IPC_MAJOR_3
/* The other core will write there its response */
dcache_invalidate_region((__sparse_force void __sparse_cache *)MAILBOX_HOSTBOX_BASE,
((struct sof_ipc_cmd_hdr *)ipc->comp_data)->size);
#endif

/*
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I would add this under #ifndef IPC4 .. to avoid any issues with IPC3.

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actually, do any IPC3 users use multicore? Obviously this only affects secondary core execution

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Good point! Mediatek and AMD uses single core, not sure about NXP

* If the primary core is waiting for secondary cores to complete, it
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