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CI CI #200: Manually run by luhenry
1d 0h 0m 4s merge-ci
merge-ci
1d 0h 0m 4s
CI CI #199: Manually run by luhenry
1d 0h 0m 4s merge-ci
merge-ci
1d 0h 0m 4s
CI CI #198: Manually run by luhenry
6m 19s merge-ci
merge-ci
6m 19s
model : don't crash on unsupported architecture (#22742) CI #197: Commit 5207d12 pushed by luhenry
1d 0h 0m 4s master
master
1d 0h 0m 4s
Merge branch 'ggml-org:master' into master CI #196: Commit 143d35e pushed by taimur-10x
1d 0h 0m 3s master
master
1d 0h 0m 3s
ggml-cpu: extend RVV quantization vec dot to higher VLENs CI #195: Pull request #10 synchronize by taimur-10x
1d 0h 0m 3s 10x/riscv-quant-vec-dot-vlens
10x/riscv-quant-vec-dot-vlens
1d 0h 0m 3s
ggml-cpu: add RVV repack GEMM and GEMV for Q3_K, Q6_K CI #194: Pull request #12 synchronize by taimur-10x
1d 0h 0m 44s 10x/riscv-quant-repack-k
10x/riscv-quant-repack-k
1d 0h 0m 44s
ggml-cpu: add RVV repack GEMM and GEMV for Q3_K, Q6_K CI #193: Pull request #12 synchronize by taimur-10x
53m 17s 10x/riscv-quant-repack-k
10x/riscv-quant-repack-k
53m 17s
ggml-cpu: extend RVV quantization vec dot to higher VLENs CI #192: Pull request #10 synchronize by taimur-10x
1d 0h 0m 3s 10x/riscv-quant-vec-dot-vlens
10x/riscv-quant-vec-dot-vlens
1d 0h 0m 3s
Merge branch 'ggml-org:master' into master CI #191: Commit 4e13bd8 pushed by taimur-10x
1d 0h 0m 2s master
master
1d 0h 0m 2s
ggml-cpu: extend RVV quantization vec dot to higher VLENs CI #190: Pull request #10 synchronize by taimur-10x
1d 0h 0m 2s 10x/riscv-quant-vec-dot-vlens
10x/riscv-quant-vec-dot-vlens
1d 0h 0m 2s
ci: Merge ubuntu-cpu-riscv64-native into ubuntu-cpu job CI #189: Commit 019b323 pushed by luhenry
1d 0h 0m 2s master
master
1d 0h 0m 2s
ci: Merge ubuntu-cpu-riscv64-native into ubuntu-cpu job CI #188: Commit d704540 pushed by luhenry
11m 0s master
master
11m 0s
Use ggml-org/ccache-action on RISC-V as well CI #187: Commit b7100c5 pushed by luhenry
1d 0h 0m 1s master
master
1d 0h 0m 1s
Use ggml-org/ccache-action on RISC-V as well CI #186: Commit 857d636 pushed by luhenry
20m 1s master
master
20m 1s
Update build-riscv.yml CI #185: Commit 6271242 pushed by luhenry
1d 0h 0m 2s master
master
1d 0h 0m 2s
CI CI #184: Manually run by luhenry
1h 4m 8s riscv64-ccache
riscv64-ccache
1h 4m 8s
vulkan: add FA dequant for q4_1, q5_0, q5_1, iq4_nl (#21029) CI #183: Commit edd4d9b pushed by taimur-10x
1d 0h 0m 2s master
master
1d 0h 0m 2s
webui : store reasoning_content so it is sent back in subsequent requ… CI #182: Commit 482192f pushed by taimur-10x
1d 0h 0m 2s master
master
1d 0h 0m 2s
CI CI #181: Manually run by luhenry
1d 0h 0m 3s ccache
ccache
1d 0h 0m 3s
CI CI #180: Manually run by luhenry
5s rise-riscv-runners
rise-riscv-runners
5s
CI CI #179: Manually run by luhenry
5s master
master
5s
Relax prefill parser to allow space. (#21240) CI #178: Commit e15efe0 pushed by taimur-10x
22h 10m 37s master
master
22h 10m 37s
CI CI #177: Manually run by luhenry
30m 46s rise-riscv-runners
rise-riscv-runners
30m 46s
CI CI #176: Manually run by luhenry
1m 54s rise-riscv-runners
rise-riscv-runners
1m 54s