Fixes for the RP1 clock driver in 6.18 #7183
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…rror Connect PLL_AUDIO_SEC to CLK_AUDIO_OUT, which had been commented out to avoid interference with I2S: we expect them never to be enabled at the same time. Work around a rounding error that occurs when the desired rate is exactly the max but not exactly achievable by the PLL. Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
PLL dividers are registered using the clk_hw in the clk_divider member of rp1_clk_desc, rather than the direct clk_hw member. In order for parent location to work, parent declarations must link to &<clock>.div.hw, not &<clock>.hw. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
In fact the register field has 6 bits, but we only ever set it to unity. Due to a typo we were setting it to BIT(1) == 2, causing PLLs to run at half the desired rate. Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
The determine_rate member of clk_ops returns the rate to the caller by modifying the pass-by-reference req structure. Its actual return value is a status code. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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See #7179 for the problems and discussion.