Pipelined 8-bit Signed Booth Multiplier (Radix-4)

📌 Overview

This repository contains an optimized hardware implementation of a Signed 8x8-bit Multiplier using Radix-4 Booth Encoding. The design features Sign Extension Elimination to reduce hardware complexity and includes input/output pipelining to ensure high-speed timing closure.

The design has been synthesized and verified in Xilinx Vivado, achieving a clock frequency of 100 MHz with significant timing slack (supporting theoretical speeds up to ~180 MHz).

🚀 Key Features

• Radix-4 Booth Encoding: Reduces the partial product count from 8 to 4, halving the adder tree depth.
• Signed Arithmetic: Natively handles 2's complement numbers.
• Sign Extension Elimination: Uses the "Inverse Sign" ($\bar{S}$) and "Hot 1" matrix trick to avoid full 16-bit sign extension for every row, saving logic resources.
• Pipelined Architecture: A 2-stage pipeline (Input Register $\to$ Logic $\to$ Output Register) ensures short critical paths.
• Verified Performance: Clean timing reports with zero violations.

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🏗️ Architecture

The design is modular, separating the encoding logic from the summation logic.

Block Hierarchy:

1. Top: The wrapper module handling clocking, reset, and I/O registration.
2. DFF: Input pipeline stage to buffer A and B operands.
3. Partial_Products: Instantiates 4 parallel Booth Encoders to generate partial product rows.
4. Partial_Products_Adder: An adder tree that sums them using the Sign Extension Elimination method.

Figure 1: Synthesis Hierarchy showing the modular structure.

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🧠 Algorithm Details

Radix-4 Booth Encoding

Instead of processing one bit at a time, we process 3 bits of the multiplier ($B_{i+1}, B_i, B_{i-1}$) to determine the operation on the multiplicand ($A$).

Multiplier Bits	Operation	Description
000, 111	$+0$	Zero
001, 010	$+A$	Add Multiplicand
011	$+2A$	Shift Left (x2)
100	$-2A$	Shift Left, Invert, Add 1
101, 110	$-A$	Invert, Add 1

Sign Extension Elimination

Standard multiplication requires sign-extending every partial product to the final width (16 bits), which wastes adder bits. This design uses the optimization constants ($\bar{S}$, $1$) placed in the MSB positions to emulate sign extension without the physical wires.

Figure 2: Radix-4 Dot Diagram illustrating the partial product alignment and sign extension strategy.

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📊 Simulation Results

The design was verified using a self-checking testbench covering corner cases (Max Positive, Max Negative, Zero).

Waveform Analysis: The simulation confirms correct signed multiplication with a 2-cycle latency (Input Reg $\to$ Output Reg).

Figure 3: Post-Synthesis Verification. Note the correct handling of negative numbers (e.g., $10 \times -2 = -20$).

Test Cases:

• $4 \times 5 = 20$
• $10 \times -2 = -20$ (Mixed Sign)
• $-10 \times -10 = 100$ (Negative $\times$ Negative)
• $127 \times 127 = 16129$ (Max Positive)
• $-128 \times 1 = -128$ (Max Negative)

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🛠️ Performance & Synthesis

The design is lightweight and timing-optimized.

Timing Summary (100 MHz)

The design meets timing constraints with ease.

• WNS (Worst Negative Slack): +4.565 ns
• WHS (Worst Hold Slack): +0.194 ns
• WPWS (Pulse Width Slack): +4.500 ns

Figure 4: Vivado Timing Summary confirming zero violations.

Power Consumption

Estimated On-Chip Power is minimal (~0.087 W), making it suitable for low-power applications.

Figure 5: Power Estimation Report.

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