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X1E GCC USB4 clock fix-ups #174

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71848fc
FROMLIST: dt-bindings: clock: qcom,x1e80100-gcc: Add missing USB4 clo…
quic-kdybcio Oct 3, 2025
bd637b6
FROMLIST: clk: qcom: gcc-x1e80100: Add missing USB4 clocks/resets
quic-kdybcio Oct 3, 2025
2ad4c60
FROMLIST: arm64: dts: qcom: x1e80100: Extend the gcc input clock list
quic-kdybcio Oct 3, 2025
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62 changes: 58 additions & 4 deletions Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -32,9 +32,36 @@ properties:
- description: PCIe 5 pipe clock
- description: PCIe 6a pipe clock
- description: PCIe 6b pipe clock
- description: USB QMP Phy 0 clock source
- description: USB QMP Phy 1 clock source
- description: USB QMP Phy 2 clock source
- description: USB4_0 QMPPHY clock source
- description: USB4_1 QMPPHY clock source
- description: USB4_2 QMPPHY clock source
- description: USB4_0 PHY DP0 GMUX clock source
- description: USB4_0 PHY DP1 GMUX clock source
- description: USB4_0 PHY PCIE PIPEGMUX clock source
- description: USB4_0 PHY PIPEGMUX clock source
- description: USB4_0 PHY SYS PCIE PIPEGMUX clock source
- description: USB4_1 PHY DP0 GMUX 2 clock source
- description: USB4_1 PHY DP1 GMUX 2 clock source
- description: USB4_1 PHY PCIE PIPEGMUX clock source
- description: USB4_1 PHY PIPEGMUX clock source
- description: USB4_1 PHY SYS PCIE PIPEGMUX clock source
- description: USB4_2 PHY DP0 GMUX 2 clock source
- description: USB4_2 PHY DP1 GMUX 2 clock source
- description: USB4_2 PHY PCIE PIPEGMUX clock source
- description: USB4_2 PHY PIPEGMUX clock source
- description: USB4_2 PHY SYS PCIE PIPEGMUX clock source
- description: USB4_0 PHY RX 0 clock source
- description: USB4_0 PHY RX 1 clock source
- description: USB4_1 PHY RX 0 clock source
- description: USB4_1 PHY RX 1 clock source
- description: USB4_2 PHY RX 0 clock source
- description: USB4_2 PHY RX 1 clock source
- description: USB4_0 PHY PCIE PIPE clock source
- description: USB4_0 PHY max PIPE clock source
- description: USB4_1 PHY PCIE PIPE clock source
- description: USB4_1 PHY max PIPE clock source
- description: USB4_2 PHY PCIE PIPE clock source
- description: USB4_2 PHY max PIPE clock source

power-domains:
description:
Expand Down Expand Up @@ -67,7 +94,34 @@ examples:
<&pcie6b_phy>,
<&usb_1_ss0_qmpphy 0>,
<&usb_1_ss1_qmpphy 1>,
<&usb_1_ss2_qmpphy 2>;
<&usb_1_ss2_qmpphy 2>,
<&usb4_0_phy_dp0_gmux_clk>,
<&usb4_0_phy_dp1_gmux_clk>,
<&usb4_0_phy_pcie_pipegmux_clk>,
<&usb4_0_phy_pipegmux_clk>,
<&usb4_0_phy_sys_pcie_pipegmux_clk>,
<&usb4_1_phy_dp0_gmux_2_clk>,
<&usb4_1_phy_dp1_gmux_2_clk>,
<&usb4_1_phy_pcie_pipegmux_clk>,
<&usb4_1_phy_pipegmux_clk>,
<&usb4_1_phy_sys_pcie_pipegmux_clk>,
<&usb4_2_phy_dp0_gmux_2_clk>,
<&usb4_2_phy_dp1_gmux_2_clk>,
<&usb4_2_phy_pcie_pipegmux_clk>,
<&usb4_2_phy_pipegmux_clk>,
<&usb4_2_phy_sys_pcie_pipegmux_clk>,
<&usb4_0_phy_rx_0_clk>,
<&usb4_0_phy_rx_1_clk>,
<&usb4_1_phy_rx_0_clk>,
<&usb4_1_phy_rx_1_clk>,
<&usb4_2_phy_rx_0_clk>,
<&usb4_2_phy_rx_1_clk>,
<&usb4_0_phy_pcie_pipe_clk>,
<&usb4_0_phy_max_pipe_clk>,
<&usb4_1_phy_pcie_pipe_clk>,
<&usb4_1_phy_max_pipe_clk>,
<&usb4_2_phy_pcie_pipe_clk>,
<&usb4_2_phy_max_pipe_clk>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
Expand Down
29 changes: 28 additions & 1 deletion arch/arm64/boot/dts/qcom/x1e80100.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -807,7 +807,34 @@
<0>,
<&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
<&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
<&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
<&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>;

power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
Expand Down
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