Glymur v8 base usb remoteproc#737
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pradyot7 wants to merge 7 commits intoqualcomm-linux:tech/all/dt/glymurfrom
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Glymur v8 base usb remoteproc#737pradyot7 wants to merge 7 commits intoqualcomm-linux:tech/all/dt/glymurfrom
pradyot7 wants to merge 7 commits intoqualcomm-linux:tech/all/dt/glymurfrom
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Document Glymur SoC bindings and Compute Reference Device (CRD) board id Link: https://lore.kernel.org/all/20260219-upstream_v3_glymur_introduction-v8-0-8ce4e489ebb6@oss.qualcomm.com/ Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Introduce the base device tree support for Glymur – Qualcomm's next-generation compute SoC. The new glymur.dtsi describes the core SoC components, including: - CPUs and CPU topology - Interrupt controller and TLMM - GCC,DISPCC and RPMHCC clock controllers - Reserved memory and interconnects - APPS and PCIe SMMU and firmware SCM - Watchdog, RPMHPD, APPS RSC and SRAM - PSCI and PMU nodes - QUPv3 serial engines - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS - PDP0 mailbox, IPCC and AOSS - Display clock controller - SPMI PMIC arbiter with SPMI0/1/2 buses - SMP2P nodes - TSENS and thermal zones (8 instances, 92 sensors) Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104, PMH0110, PMIC's along with temp-alarm and GPIO nodes needed on Glymur Enabled PCIe controllers and associated PHY to support boot to shell with nvme storage, List of PCIe instances enabled: - PCIe3b - PCIe4 - PCIe5 - PCIe6 Link: https://lore.kernel.org/all/20260219-upstream_v3_glymur_introduction-v8-0-8ce4e489ebb6@oss.qualcomm.com/ Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Co-developed-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com> Co-developed-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Co-developed-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Co-developed-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Co-developed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Co-developed-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add initial device tree support for the Glymur Compute Reference Device(CRD) board, with this board dts glymur crd can boot to shell with rootfs on nvme and uart21 as serial console Features enabled are: - Board and sleep clocks - Volume up/down keys - Regulators 0 - 4 - Power supplies and sideband signals (PERST, WAKE, CLKREQ) for PCIe3b/4/5/6 controllers and PHYs Link: https://lore.kernel.org/all/20260219-upstream_v3_glymur_introduction-v8-0-8ce4e489ebb6@oss.qualcomm.com/ Co-developed-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Co-developed-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Co-developed-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
The Glymur USB system contains 3 USB type C ports, 1 USB multiport controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS DWC3 based, so describe them as flattened DWC3 QCOM nodes. Link: https://lore.kernel.org/linux-arm-msm/20260223-dts-qcom-glymur-add-usb-support-v2-1-f4e0f38db21d@oss.qualcomm.com/ Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Tested-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
The Qualcomm Glymur Compute Reference Device comes with 3 Type-C ports, one USB Type-A, and a fingerprint reader connected over USB. Each of these 3 Type-C ports are connected to one of the USB combo PHYs and one of the M31 eUSB2 PHYs. The Type-A is connected to the USB Multi-port controller via one of the M31 eUSB2 PHYs and one USB3 UNI PHY. The fingerprint reader is connected to the USB_2 controller. All M31 eUSB2 PHYs have associated eUSB2 to USB 2.0 repeaters, which are either part of SMB2370 PMICs or dedicated NXP PTN3222. So enable all needed controllers, PHYs and repeaters, while describing their supplies. Also describe the PMIC glink graph for Type-C connectors. Link: https://lore.kernel.org/linux-arm-msm/20260223-dts-qcom-glymur-add-usb-support-v2-1-f4e0f38db21d@oss.qualcomm.com/ Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Tested-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add remoteproc PAS loader for ADSP and CDSP with its fastrpc nodes. Link: https://lore.kernel.org/lkml/20260129001358.770053-5-sibi.sankar@oss.qualcomm.com/ Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Enable ADSP and CDSP on Glymur CRD board. Link: https://lore.kernel.org/lkml/20260129001358.770053-6-sibi.sankar@oss.qualcomm.com/ Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
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Glymur v8 base usb remoteproc