regulator: qcom_usb_vbus: add support for qcom,pm4125-vbus-reg#1115
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regulator: qcom_usb_vbus: add support for qcom,pm4125-vbus-reg#1115kotarake wants to merge 96 commits into
kotarake wants to merge 96 commits into
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Document the IDs used by Shikra SoC IoT variants: - CQ2390M: Shikra Retail with modem - CQ2390S: Shikra Retail without modem - IQ2390S: Shikra Industrial without modem Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add SoC ID for Shikra IoT variants: CQ2390M, CQ2390S and IQ2390S. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Qualcomm Shikra SoC implements arm,mmu-500. Document its compatible. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the SCM compatible on the Shikra SoC. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the device tree binding for the Shikra EVK platform, which is built around a modular System-on-Module (SoM) mounted on a common carrier board. The SoM integrates the Shikra SoC, PMICs, and essential GPIOs, while the EVK carrier board provides additional peripherals such as UART and USB interfaces. Shikra EVK supports three SoM variants: retail with modem, retail without modem, and an industrial non-modem variant. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add compatible for Shikra SoC IMEM. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the Top Level Mode Multiplexer on the Shikra platform. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add pinctrl driver for TLMM block found in the Shikra SoC. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the RPM Power Domains on the Shikra Platform. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Shikra has the same RPM power domains as QCM2290. Add shikra support by reusing QCM2290 power domains. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Document the pm8150 compatible string and available regulators in the QCOM SMD RPM regulator documentation. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
The PM8150 is found on boards with shikra SoCs and It provides 10 SMPS and 18 LDO regulators. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Add the rpmpd compatable string for shikra. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Qualcomm Shikra SoC implements qcom,smmu-500 for adreno-smmu. Document its corresponding compatible. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add "qcom,shikra-apcs-hmss-global" compatibility string in qcom_apcs_ipc mailbox driver to match apcs_glb device node. Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Document compatible string for the QFPROM on Shikra platform. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add the qcom,shikra-rpm-proc compatible string to the Qualcomm RPM remote processor device tree binding. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add compatible for the Qualcomm Shikra APCS block to the Qualcomm APCS binding. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the compatible for Shikra. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the qcom,rpmcc-shikra compatible. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add support for qcom global clock controller bindings for Shikra platform. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add support for RPM-managed clocks on the Shikra platform. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add support for Global clock controller for Shikra Qualcomm SoC. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Enable the GCC driver on the Qualcomm Shikra EVK boards. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add devicetree binding for watchdog present on Qualcomm's Shikra SoC. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the GPI DMA engine on Shikra platform. Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Update dt-bindings to add Shikra to QMP Phy list. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Update dt-bindings to add Shikra to QUSB2 Phy list. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Introduce the compatible definition for Shikra QCOM SNPS DWC3. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Add init sequence and phy configuration for Shikra. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
The raw formats supported by Iris were previously advertised unconditionally, assuming UBWC support on all platforms. However, some platforms do not support UBWC which results in incorrect format capability exposure. Use the UBWC configuration provided by the platform to dynamically filter raw formats at runtime. If UBWC is not supported, UBWC-based formats are omitted from the advertised capability list, while linear formats remain available. Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
The set_preset_registers sequence is currently shared across all supported devices. Starting with Qualcomm QCM2290 (AR50LT), the register programming would differ. Move set_preset_register into a vpu_op to allow per-device customization. This change prepares the driver for upcoming hardware variants. No functional change so far for existing devices. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
The interrupt_init sequence is currently shared across all supported devices. Starting with Qualcomm QCM2290 (AR50LT), the register programming would differ. Move interrupt_init into a vpu_op to allow per-device customization. This change prepares the driver for upcoming hardware variants. No functional change so far for existing devices. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
On AR50LT platforms AbsolutelyPerfectRouting (ARP) needs to be disabled so firmware can configure the ARP internal buffer as non-secure for encoder usage. In preparation of adding support for AR50LT platforms, add an optional disable_arp callback to the VPU ops and invoke it from core init and resume paths. No functional change for existing platforms. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
For AR50LT core, the value of WRAPPER_INTR_STATUS_A2HWD_BMASK differs from the currently supported VPUs. In preparation for adding AR50LT support in subsequent patches, introduce a platform data field, wd_intr_mask, to capture the watchdog interrupt bitmask per platform. Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
AR50LT require explicit instantaneous bandwidth (IB) voting in addition to average bandwidth (AB) when configuring interconnect QoS. This requirement is due to QSB (Qualcomm System Bus) 128b to QNS ( Qualcomm Network Switch) 256b conversion at video noc in AR50LT which is not needed for other IRIS cores. In preparation of adding support for AR50LT core, introduce platform-configurable IB multiplier and enable IB voting for all SoCs. Existing platforms default to IB == AB, while AR50LT requires 2x peak bandwidth. Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Add power sequence for ar5lt core. Add register handling for ar50lt by hooking up vpu op with ar50lt specific implementation or reuse from earlier generation wherever feasible. Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Introduces AR50LT buffer size calculation for both encoder and decoder. Reuse the buffer size calculation which are common, while adding the AR50LT specific ones separately. Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Add support for the qcm2290 SoC by introducing a new compatible string for the AR50LT core and the corresponding platform data. This change: - Adds qcm2290 as a supported compatible for the AR50LT core. - Introduces AR50LT-specific platform data describing VPU configuration. - Adds a qcm2290-specific header describing firmware capabilities. Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Document the Iris video accelerator used on Shikra platforms by adding the qcom,shikra-iris compatible. Although QCM2290 and Shikra share the same video hardware and overall integration, their SMMU programming differs. QCM2290 exposes separate Stream IDs for the video hardware and the Xtensa path, requiring two explicit IOMMU entries, whereas Shikra uses a masked SMR to collapse equivalent Stream IDs into a single mapping. Due to QCM2290’s SID layout and Xtensa isolation requirements, such SMR masking is not applicable on QCM2290 platforms. Since Shikra uses the same video hardware as QCM2290 and shares the same programming model and capabilities, it is added as a fallback compatible to qcom,qcm2290-venus, with conditional handling to allow either one or two IOMMU entries. Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
QCM2290 is currently supported by the Venus driver using HFI Gen1. However, support for this platform is being added to the Iris driver, where it will be preferred going forward, initially using HFI Gen2 and eventually providing support for both Gen1 and Gen2. As part of early enablement for the Shikra platform, which reuses the qcm2290 compatible as a fallback, it is necessary to allow the Iris driver to bind to this hardware instead of Venus when Iris support is enabled in the kernel configuration. Introduce a configuration-based guard to prevent the Venus driver from registering qcm2290 support when CONFIG_VIDEO_QCOM_IRIS is enabled. This ensures that the Iris driver is selected for QCM2290/Shikra platforms in early development kernels, without changing the default behavior when Iris is not enabled. This change is intended as an intermediate step for early bring-up. Full HFI Gen1 support in the Iris driver will be added before posting the final upstream series. Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Map the wakeup capable GPIOs to respective MPM pins for shikra. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
Set `qos_mode` on Shikra interconnect master nodes and mark ap-owned masters with `ap_owned` where missing. This enables correct QoS register programming (fixed or bypass mode) for the defined QoS ports. Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Document the Last Level Cache Controller on Shikra SoC. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
The partitions array is currently statically sized and uses the remote host ID as an index. Future protocol improvements to allow for more than two hosts in a partition will require hostIDs to be bitwise significant integers. This will result in large, sparse host IDs that generally exceed the current static limit. Switch to using xarray to efficiently handle these sparse indices and allow for dynamic growth. Signed-off-by: Tony Truong <tony.truong@oss.qualcomm.com> Signed-off-by: Pranav Mahesh Phansalkar <pranav.phansalkar@oss.qualcomm.com> Tested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> # Glymur CRD Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260410-smem-v1-1-8e94bb5416a6@oss.qualcomm.com
The wakeup enable bit needs to be set irrespective of the SoC using PDC or MPM as wakeup capable irqchip to allow the GPIO interrupts to be forwarded to parent irqchip. This is set only for PDC irqchip using additional check skip_wake_irqs making it impossible for MPM irqchip to detect the GPIO interrupt during SoC low power mode since for MPM irqchip the skip_wake_irqs is always false. Remove skip_wake_irqs condition when setting wakeup enable bit to allow forwarding GPIO interrupts for SoCs using MPM irqchip too. Fixes: 76b446f ("pinctrl: qcom: handle intr_target_reg wakeup_present/enable bits") Link: https://lore.kernel.org/all/20260430-enable_wakeup_capable_gpios-v2-1-8c26ac795318@oss.qualcomm.com Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Reviewed-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
Add DSP and lpaicp Peripheral Authentication Service support for the Shikra platform. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add devicetree binding documentation for the Qualcomm Shikra SoC Peripheral Authentication Service (PAS) remoteproc nodes. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add GCC_QUSB2PHY_SEC_BCR reset support for Shikra platform. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add GCC_QUSB2PHY_SEC_BCR reset support for Shikra. While at it, drop the flags which are not required for the fixed parent clocks. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Remove the unused enum entry to keep the binding indices aligned with device tree. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
jprakash-qc
reviewed
May 12, 2026
| // Qualcomm PMIC VBUS output regulator driver | ||
| // | ||
| // Copyright (c) 2020, The Linux Foundation. All rights reserved. | ||
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| .probe = qcom_usb_vbus_regulator_probe, | ||
| }; | ||
| module_platform_driver(qcom_usb_vbus_regulator_driver); | ||
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| static const struct of_device_id qcom_usb_vbus_regulator_match[] = { | ||
| { .compatible = "qcom,pm8150b-vbus-reg" }, | ||
| { .compatible = "qcom,pm8150b-vbus-reg", .data = &pm8150b_data }, | ||
| { .compatible = "qcom,pm4125-vbus-reg", .data = &pm4125_data }, |
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Please add a documentation change also and make sure to mention in its commit message why the new compatible is needed.
I think the voltage properties for this peripheral should also now be
regulator-min-microvolt/regulator-max-microvolt
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i will update the documentation as well in next patch set
| #define PM4125_CMD_OTG 0x50 | ||
| #define PM4125_VBOOST_CFG 0x52 | ||
| #define PM4125_VBOOST_CFG_MASK GENMASK(1, 0) | ||
| #define PM4125_OTG_CFG 0x56 |
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I see you are using OTG_EN_SRC_CFG (BIT(1)) when writing into this register, but I think it should be BIT (0) when checking IPCAT. Can you please check this again?
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ACK , i will update this next patch set
jprakash-qc
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May 12, 2026
| regulator will be enabled in situations where the device is required to | ||
| provide power to the connected peripheral. | ||
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| The pm8150b variant uses an OTG current-limit selector at register 0x52, |
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You don't need to mention the exact register....you can remove this:
"at register 0x52"
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ACK, i will update in the next patch
| 3000 mA. | ||
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| The pm4125 variant uses a different register layout CMD_OTG is at 0x50, | ||
| OTG_CFG is at 0x56, and register 0x52 is a 2-bit VBOOST voltage selector |
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s/CMD_OTG is at 0x50, OTG_CFG is at 0x56, and register 0x52 is a 2-bit VBOOST voltage selector/ with a 2-bit VBOOST voltage selector
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ACK, i will update in the next patch
| required: | ||
| - regulator-min-microamp | ||
| - regulator-max-microamp | ||
|
|
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I think you may also need to add another condition for qcom,pm4125-vbus-reg, so that if it is used, it has these properties under it:
regulator-min-microvolt
regulator-max-microvolt
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ACK, i will update in the next patch
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| usb-vbus-regulator@5000 { | ||
| compatible = "qcom,pm4125-vbus-reg"; | ||
| reg = <0x5000>; |
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I think you need to add these here:
regulator-min-microvolt
regulator-max-microvolt
Or is it not needed?
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ACK, i will update the next patch
…-reg The pm4125 PMIC uses a different USB VBUS register layout than pm8150b. It uses a 2-bit VBOOST voltage selector supporting output voltages of 4.25 V, 4.5 V, 4.75 V and 5.0 V, instead of a current-limit selector. Move qcom,pm4125-vbus-reg from the pm8150b fallback items list into the standalone enum since the driver handles it with its own match-data and register layout. Make regulator-min/max-microamp conditional so they are only required for current-limit variants (pm8150b, pm6150, pm7250b, pmi632). Add an if/then condition for qcom,pm4125-vbus-reg requiring regulator-min/ max-microvolt instead, and update the pm4125 example accordingly. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
The PM4125 PMIC uses a different register layout for USB VBUS control compared to PM8150B. On PM4125, CMD_OTG is at offset 0x50, OTG_CFG is at 0x56, and offset 0x52 is a 2-bit VBOOST voltage selector rather than a current-limit selector. Introduce per-compatible regulator descriptor data to accommodate these differences. This keeps the existing PM8150B current-limit logic intact while adding a dedicated voltage-selector path for PM4125. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
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The PM4125 PMIC uses a different register layout for USB VBUS control compared to PM8150B. On PM4125, CMD_OTG is at offset 0x50, OTG_CFG is at 0x56, and offset 0x52 is a 2-bit VBOOST voltage selector rather than a current-limit selector.
Introduce per-compatible regulator descriptor data to accommodate these differences. This keeps the existing PM8150B current-limit logic intact while adding a dedicated voltage-selector path for PM4125.