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PPC debugger XML support #1600

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Merged
xwings merged 4 commits into from
Nov 5, 2025
Merged

PPC debugger XML support #1600

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29c552e
add ppc xml basic target , add a no yield coverage
Nov 4, 2025
8d52304
Merge remote-tracking branch 'origin/dev'
Nov 4, 2025
4810ad7
ppc xml fix
0xMirasio Nov 4, 2025
08650be
remove hashable drcov bb_entries
0xMirasio Nov 5, 2025
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4 changes: 3 additions & 1 deletion qiling/debugger/gdb/gdb.py
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Original file line number Diff line number Diff line change
Expand Up @@ -183,6 +183,7 @@ def handle_qmark(subcmd: str) -> Reply:
from unicorn.arm_const import UC_ARM_REG_R11
from unicorn.arm64_const import UC_ARM64_REG_X29
from unicorn.mips_const import UC_MIPS_REG_INVALID
from unicorn.ppc_const import UC_PPC_REG_31

arch_uc_bp = {
QL_ARCH.X86 : UC_X86_REG_EBP,
Expand All @@ -191,7 +192,8 @@ def handle_qmark(subcmd: str) -> Reply:
QL_ARCH.ARM64 : UC_ARM64_REG_X29,
QL_ARCH.MIPS : UC_MIPS_REG_INVALID, # skipped
QL_ARCH.A8086 : UC_X86_REG_EBP,
QL_ARCH.CORTEX_M : UC_ARM_REG_R11
QL_ARCH.CORTEX_M : UC_ARM_REG_R11,
QL_ARCH.PPC : UC_PPC_REG_31
}[self.ql.arch.type]

def __get_reg_idx(ucreg: int) -> int:
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51 changes: 51 additions & 0 deletions qiling/debugger/gdb/xml/ppc/ppc-core.xml
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@@ -0,0 +1,51 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2007-2020 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->

<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.power.core">
<reg name="r0" bitsize="32" type="uint32"/>
<reg name="r1" bitsize="32" type="uint32"/>
<reg name="r2" bitsize="32" type="uint32"/>
<reg name="r3" bitsize="32" type="uint32"/>
<reg name="r4" bitsize="32" type="uint32"/>
<reg name="r5" bitsize="32" type="uint32"/>
<reg name="r6" bitsize="32" type="uint32"/>
<reg name="r7" bitsize="32" type="uint32"/>
<reg name="r8" bitsize="32" type="uint32"/>
<reg name="r9" bitsize="32" type="uint32"/>
<reg name="r10" bitsize="32" type="uint32"/>
<reg name="r11" bitsize="32" type="uint32"/>
<reg name="r12" bitsize="32" type="uint32"/>
<reg name="r13" bitsize="32" type="uint32"/>
<reg name="r14" bitsize="32" type="uint32"/>
<reg name="r15" bitsize="32" type="uint32"/>
<reg name="r16" bitsize="32" type="uint32"/>
<reg name="r17" bitsize="32" type="uint32"/>
<reg name="r18" bitsize="32" type="uint32"/>
<reg name="r19" bitsize="32" type="uint32"/>
<reg name="r20" bitsize="32" type="uint32"/>
<reg name="r21" bitsize="32" type="uint32"/>
<reg name="r22" bitsize="32" type="uint32"/>
<reg name="r23" bitsize="32" type="uint32"/>
<reg name="r24" bitsize="32" type="uint32"/>
<reg name="r25" bitsize="32" type="uint32"/>
<reg name="r26" bitsize="32" type="uint32"/>
<reg name="r27" bitsize="32" type="uint32"/>
<reg name="r28" bitsize="32" type="uint32"/>
<reg name="r29" bitsize="32" type="uint32"/>
<reg name="r30" bitsize="32" type="uint32"/>
<reg name="r31" bitsize="32" type="uint32"/>

<reg name="cr" bitsize="32" type="uint32"/>
<reg name="lr" bitsize="32" type="code_ptr"/>
<reg name="pc" bitsize="32" type="code_ptr"/>
<reg name="msr" bitsize="32" type="uint32"/>
<reg name="ctr" bitsize="32" type="uint32"/>
<reg name="xer" bitsize="32" type="uint32"/>


</feature>
12 changes: 12 additions & 0 deletions qiling/debugger/gdb/xml/ppc/target.xml
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Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2009-2016 Free Software Foundation, Inc.

*!Copying and distribution of this file, with or without modification,
*!are permitted in any medium without royalty provided the copyright
*!notice and this notice are preserved. -->

<!DOCTYPE target SYSTEM "gdb-target.dtd">
<target xmlns:xi="http://www.w3.org/2001/XInclude">
<architecture>powerpc:common</architecture>
<xi:include href="ppc-core.xml"/>
</target>
7 changes: 6 additions & 1 deletion qiling/debugger/gdb/xmlregs.py
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Expand Up @@ -38,6 +38,10 @@
reg_map_ymm as x86_regs_ymm
)

from qiling.arch.ppc_const import (
reg_map as ppc_regs
)

from qiling.const import QL_ARCH, QL_OS

RegEntry = Tuple[Optional[int], int, int]
Expand Down Expand Up @@ -142,7 +146,8 @@ def __load_regsmap(archtype: QL_ARCH, xmltree: ElementTree.ElementTree) -> Seque
QL_ARCH.ARM: dict(**arm_regs, **arm_regs_vfp, **arm_regs_q, **arm_regs_s),
QL_ARCH.CORTEX_M: dict(**cortex_m_regs),
QL_ARCH.ARM64: dict(**arm64_regs, **arm64_regs_v, **arm64_reg_map_fp),
QL_ARCH.MIPS: dict(**mips_regs_gpr)
QL_ARCH.MIPS: dict(**mips_regs_gpr),
QL_ARCH.PPC: dict(**ppc_regs)
}[archtype]

regsinfo = sorted(QlGdbFeatures.__walk_xml_regs(xmltree))
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