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Added the needed rtl for the exercise #91

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9d810f6
Added the needed rtl for the exercise
yousefkhaled1750 Mar 16, 2023
323fed2
added the AXI IP modifications
yousefkhaled1750 Mar 22, 2023
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1 change: 1 addition & 0 deletions Bender.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,7 @@ dependencies:
hwpe-mac-engine: { git: "https://github.com/pulp-platform/hwpe-mac-engine.git", version: 1.3.3 }
riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.5.0 }
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.1 }
wide_alu_ip: { git: "https://github.com/yousefjoe175/wide_alu_ip.git", rev: "d80ffe4c92dae26cf1c6b6acc487721ad09d9551" }

sources:
# pulp_soc
Expand Down
52 changes: 48 additions & 4 deletions rtl/pulp_soc/l2_ram_multi_bank.sv
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Expand Up @@ -11,23 +11,30 @@
`include "soc_mem_map.svh"

module l2_ram_multi_bank #(
parameter NB_BANKS = 4,
parameter int unsigned BANK_SIZE_INTL_SRAM = 32768 //Number of 32-bit words
// parameter NB_BANKS = 4,
// parameter int unsigned BANK_SIZE_INTL_SRAM = 32768 //Number of 32-bit words

parameter NB_BANKS = 8, // for the memlayout exercise (interleaved)
parameter int unsigned BANK_SIZE_INTL_SRAM = 2*32768 // for the memlayout exercise (interleaved)

) (
input logic clk_i,
input logic rst_ni,
input logic init_ni,
input logic test_mode_i,
XBAR_TCDM_BUS.Slave mem_slave[NB_BANKS],
XBAR_TCDM_BUS.Slave mem_pri_slave[2]
XBAR_TCDM_BUS.Slave mem_pri_slave[2],
XBAR_TCDM_BUS.Slave additional_pri_slave
);
localparam int unsigned BANK_SIZE_PRI0 = 8192; //Number of 32-bit words
localparam int unsigned BANK_SIZE_PRI1 = 8192; //Number of 32-bit words
localparam int unsigned BANK_SIZE_PRI2 = 8192; //Number of 32-bit words /****** change for the memlayout exercies ******/

//Derived parameters
localparam int unsigned INTL_MEM_ADDR_WIDTH = $clog2(BANK_SIZE_INTL_SRAM);
localparam int unsigned PRI0_MEM_ADDR_WIDTH = $clog2(BANK_SIZE_PRI0);
localparam int unsigned PRI1_MEM_ADDR_WIDTH = $clog2(BANK_SIZE_PRI1);
localparam int unsigned PRI2_MEM_ADDR_WIDTH = $clog2(BANK_SIZE_PRI2); /****** change for the memlayout exercies ******/

//Used in testbenches

Expand Down Expand Up @@ -114,7 +121,7 @@ module l2_ram_multi_bank #(
assign pri1_address = mem_pri_slave[1].add - `SOC_MEM_MAP_PRIVATE_BANK1_START_ADDR;

tc_sram #(
.NumWords ( BANK_SIZE_PRI1 ),
.NumWords ( BANK_SIZE_PRI2 ),
.DataWidth ( 32 ),
.NumPorts ( 1 ),
.Latency ( 1 )
Expand All @@ -130,4 +137,41 @@ module l2_ram_multi_bank #(
);



// Additional Bank for exercise
//Perform TCDM handshaking for constant 1 cycle latency
assign additional_pri_slave.gnt = additional_pri_slave.req;
assign additional_pri_slave.r_opc = 1'b0;
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
additional_pri_slave.r_valid <= 1'b0;
end else begin
additional_pri_slave.r_valid <= additional_pri_slave.req;
end
end
//Remove Address offset
logic [31:0] pri2_address;
assign pri2_address = additional_pri_slave.add - `SOC_MEM_MAP_EXERCISE_BANK_START_ADDR;

tc_sram #(
.NumWords ( BANK_SIZE_PRI2 ),
.DataWidth ( 32 ),
.NumPorts ( 1 ),
.Latency ( 1 )
) bank_sram_pri2_i (
.clk_i,
.rst_ni,
.req_i ( additional_pri_slave.req ),
.we_i ( ~additional_pri_slave.wen ),
.addr_i ( pri2_address[PRI2_MEM_ADDR_WIDTH+1:2] ), //Convert from byte to word addressing
.wdata_i ( additional_pri_slave.wdata ),
.be_i ( additional_pri_slave.be ),
.rdata_o ( additional_pri_slave.r_rdata )
);






endmodule // l2_ram_multi_bank
43 changes: 35 additions & 8 deletions rtl/pulp_soc/pulp_soc.sv
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Expand Up @@ -216,7 +216,8 @@ module pulp_soc import dm::*; #(
localparam NB_L2_BANKS = `NB_L2_CHANNELS;
//The L2 parameter do not influence the size of the memories. Change them in the l2_ram_multibank. This parameters
//are only here to save area in the uDMA by only storing relevant bits.
localparam L2_BANK_SIZE = 32768; // in 32-bit words
//localparam L2_BANK_SIZE = 32768; // in 32-bit words
localparam L2_BANK_SIZE = 32768*2; /****** change for the memlayout exercies ******/
localparam L2_MEM_ADDR_WIDTH = $clog2(L2_BANK_SIZE * NB_L2_BANKS) - $clog2(NB_L2_BANKS); // 2**L2_MEM_ADDR_WIDTH rows (64bit each) in L2 --> TOTAL L2 SIZE = 8byte * 2^L2_MEM_ADDR_WIDTH
localparam NB_L2_BANKS_PRI = 2;

Expand Down Expand Up @@ -377,6 +378,14 @@ module pulp_soc import dm::*; #(
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) s_data_out_bus ();

/* AXI bus for the AXI IP (exercise) */
AXI_BUS #(
.AXI_ADDR_WIDTH ( 32),
.AXI_DATA_WIDTH ( 32),
.AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) s_wide_alu_bus ();

//assign s_data_out_bus.aw_atop = 6'b0;

FLL_BUS s_soc_fll_master ();
Expand All @@ -388,6 +397,7 @@ module pulp_soc import dm::*; #(
APB_BUS s_apb_periph_bus ();

XBAR_TCDM_BUS s_mem_rom_bus ();
XBAR_TCDM_BUS s_mem_exercise_bus (); /***** exercise ******/

XBAR_TCDM_BUS s_mem_l2_bus[NB_L2_BANKS-1:0]();
XBAR_TCDM_BUS s_mem_l2_pri_bus[NB_L2_BANKS_PRI-1:0]();
Expand Down Expand Up @@ -548,12 +558,13 @@ module pulp_soc import dm::*; #(
.NB_BANKS ( NB_L2_BANKS ),
.BANK_SIZE_INTL_SRAM ( L2_BANK_SIZE )
) l2_ram_i (
.clk_i ( s_soc_clk ),
.rst_ni ( s_soc_rstn ),
.init_ni ( 1'b1 ),
.test_mode_i ( dft_test_mode_i ),
.mem_slave ( s_mem_l2_bus ),
.mem_pri_slave ( s_mem_l2_pri_bus )
.clk_i ( s_soc_clk ),
.rst_ni ( s_soc_rstn ),
.init_ni ( 1'b1 ),
.test_mode_i ( dft_test_mode_i ),
.mem_slave ( s_mem_l2_bus ),
.mem_pri_slave ( s_mem_l2_pri_bus ),
.additional_pri_slave ( s_mem_exercise_bus ) /****** exercise *****/
);


Expand Down Expand Up @@ -855,9 +866,25 @@ module pulp_soc import dm::*; #(
.apb_peripheral_bus ( s_apb_periph_bus ),
.l2_interleaved_slaves ( s_mem_l2_bus ),
.l2_private_slaves ( s_mem_l2_pri_bus ),
.boot_rom_slave ( s_mem_rom_bus )
.boot_rom_slave ( s_mem_rom_bus ),
.additional_pri_slave ( s_mem_exercise_bus ), /***** exercise *****/
.wide_alu_slave ( s_wide_alu_bus )
);

/* Instantiation of the AXI IP (exercise) */
wide_alu_top #(
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_ID_WIDTH(AXI_ID_OUT_WIDTH),
.AXI_USER_WIDTH(AXI_USER_WIDTH)
)i_wide_alu (
.clk_i(s_soc_clk),
.rst_ni(s_soc_rstn),
.test_mode_i(dft_test_mode_i),
.axi_slave(s_wide_alu_bus)
)



/* Debug Subsystem */

dmi_jtag #(
Expand Down
39 changes: 24 additions & 15 deletions rtl/pulp_soc/soc_interconnect_wrap.sv
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Expand Up @@ -30,7 +30,8 @@ module soc_interconnect_wrap
import pkg_soc_interconnect::addr_map_rule_t;
#(
parameter int NR_HWPE_PORTS = 0,
parameter int NR_L2_PORTS = 4,
//parameter int NR_L2_PORTS = 4,
parameter int NR_L2_PORTS = 8, //memlayout exercise (interleaved)
// AXI Input Plug
localparam int AXI_IN_ADDR_WIDTH = 32, // All addresses in the SoC must be 32-bit
localparam int AXI_IN_DATA_WIDTH = 64, // The internal AXI->TCDM protocol converter does not support any other
Expand All @@ -44,7 +45,7 @@ module soc_interconnect_wrap
) (
input logic clk_i,
input logic rst_ni,
input logic test_en_i,
input logic test_en_i, //(XBAR_TCDM_BUS) exists in components/pulp_interfaces.sv
XBAR_TCDM_BUS.Slave tcdm_fc_data, //Data Port of the Fabric Controller
XBAR_TCDM_BUS.Slave tcdm_fc_instr, //Instruction Port of the Fabric Controller
XBAR_TCDM_BUS.Slave tcdm_udma_tx, //TX Channel for the uDMA
Expand All @@ -56,7 +57,9 @@ module soc_interconnect_wrap
APB_BUS.Master apb_peripheral_bus, // Connects to all the SoC Peripherals
XBAR_TCDM_BUS.Master l2_interleaved_slaves[NR_L2_PORTS], // Connects to the interleaved memory banks
XBAR_TCDM_BUS.Master l2_private_slaves[2], // Connects to core-private memory banks
XBAR_TCDM_BUS.Master boot_rom_slave //Connects to the bootrom
XBAR_TCDM_BUS.Master boot_rom_slave, //Connects to the bootrom
XBAR_TCDM_BUS.Master additional_pri_slave, //connects to the exercise memory
AXI_BUS.Master wide_alu_slave //connects to the AXI IP exercise (note it's master as the slave is the IP itself)
);

//**Do not change these values unles you verified that all downstream IPs are properly parametrized and support it**
Expand Down Expand Up @@ -92,12 +95,13 @@ module soc_interconnect_wrap
////////////////////////////////////////
// Address Rules for the interconnect //
////////////////////////////////////////
localparam NR_RULES_L2_DEMUX = 3;
localparam NR_RULES_L2_DEMUX = 4; /***** exerciese ******/
//Everything that is not routed to port 1 or 2 ends up in port 0 by default
localparam addr_map_rule_t [NR_RULES_L2_DEMUX-1:0] L2_DEMUX_RULES = '{
'{ idx: 1 , start_addr: `SOC_MEM_MAP_PRIVATE_BANK0_START_ADDR , end_addr: `SOC_MEM_MAP_PRIVATE_BANK1_END_ADDR} , //Both , bank0 and bank1 are in the same address block
'{ idx: 1 , start_addr: `SOC_MEM_MAP_BOOT_ROM_START_ADDR , end_addr: `SOC_MEM_MAP_BOOT_ROM_END_ADDR} ,
'{ idx: 2 , start_addr: `SOC_MEM_MAP_TCDM_START_ADDR , end_addr: `SOC_MEM_MAP_TCDM_END_ADDR }};
'{ idx: 1 , start_addr: `SOC_MEM_MAP_PRIVATE_BANK0_START_ADDR , end_addr: `SOC_MEM_MAP_PRIVATE_BANK1_END_ADDR} , //Both , bank0 and bank1 are in the same address block
'{ idx: 1 , start_addr: `SOC_MEM_MAP_BOOT_ROM_START_ADDR , end_addr: `SOC_MEM_MAP_BOOT_ROM_END_ADDR} ,
'{ idx: 1 , start_addr: `SOC_MEM_MAP_EXERCISE_BANK_START_ADDR , end_addr: `SOC_MEM_MAP_EXERCISE_BANK_END_ADDR} , /***** exerciese ******/
'{ idx: 2 , start_addr: `SOC_MEM_MAP_TCDM_START_ADDR , end_addr: `SOC_MEM_MAP_TCDM_END_ADDR }};

localparam NR_RULES_INTERLEAVED_REGION = 1;
localparam addr_map_rule_t [NR_RULES_INTERLEAVED_REGION-1:0] INTERLEAVED_ADDR_SPACE = '{
Expand All @@ -107,12 +111,14 @@ module soc_interconnect_wrap
localparam addr_map_rule_t [NR_RULES_CONTIG_CROSSBAR-1:0] CONTIGUOUS_CROSSBAR_RULES = '{
'{ idx: 0 , start_addr: `SOC_MEM_MAP_PRIVATE_BANK0_START_ADDR , end_addr: `SOC_MEM_MAP_PRIVATE_BANK0_END_ADDR} ,
'{ idx: 1 , start_addr: `SOC_MEM_MAP_PRIVATE_BANK1_START_ADDR , end_addr: `SOC_MEM_MAP_PRIVATE_BANK1_END_ADDR} ,
'{ idx: 2 , start_addr: `SOC_MEM_MAP_BOOT_ROM_START_ADDR , end_addr: `SOC_MEM_MAP_BOOT_ROM_END_ADDR}};
'{ idx: 2 , start_addr: `SOC_MEM_MAP_BOOT_ROM_START_ADDR , end_addr: `SOC_MEM_MAP_BOOT_ROM_END_ADDR} ,
'{ idx: 3 , start_addr: `SOC_MEM_MAP_EXERCISE_BANK_START_ADDR , end_addr: `SOC_MEM_MAP_EXERCISE_BANK_END_ADDR}}; /****** exercise *****/

localparam NR_RULES_AXI_CROSSBAR = 2;
localparam addr_map_rule_t [NR_RULES_AXI_CROSSBAR-1:0] AXI_CROSSBAR_RULES = '{
'{ idx: 0, start_addr: `SOC_MEM_MAP_AXI_PLUG_START_ADDR, end_addr: `SOC_MEM_MAP_AXI_PLUG_END_ADDR},
'{ idx: 1, start_addr: `SOC_MEM_MAP_PERIPHERALS_START_ADDR, end_addr: `SOC_MEM_MAP_PERIPHERALS_END_ADDR}};
'{ idx: 1, start_addr: `SOC_MEM_MAP_PERIPHERALS_START_ADDR, end_addr: `SOC_MEM_MAP_PERIPHERALS_END_ADDR}
'{ idx: 2, start_addr: `SOC_MEM_MAP_WIDE_ALU_START_ADDR, end_addr: `SOC_MEM_MAP_WIDE_ALU_END_ADDR}}; /* modified for AXI IP exercise */

//For legacy reasons, the fc_data port can alias the address prefix 0x000 to 0x1c0. E.g. an access to 0x00001234 is
//mapped to 0x1c001234. The following lines perform this remapping.
Expand Down Expand Up @@ -166,18 +172,20 @@ module soc_interconnect_wrap
`TCDM_ASSIGN_INTF(master_ports[`NR_SOC_TCDM_MASTER_PORTS + i], axi_bridge_2_interconnect[i])
end

XBAR_TCDM_BUS contiguous_slaves[3]();
XBAR_TCDM_BUS contiguous_slaves[4](); /***** exerciese ******/
`TCDM_ASSIGN_INTF(l2_private_slaves[0], contiguous_slaves[0])
`TCDM_ASSIGN_INTF(l2_private_slaves[1], contiguous_slaves[1])
`TCDM_ASSIGN_INTF(boot_rom_slave, contiguous_slaves[2])
`TCDM_ASSIGN_INTF(additional_pri_slave, contiguous_slaves[3]) /***** exerciese ******/

AXI_BUS #(.AXI_ADDR_WIDTH(32),
.AXI_DATA_WIDTH(32),
.AXI_ID_WIDTH(pkg_soc_interconnect::AXI_ID_OUT_WIDTH),
.AXI_USER_WIDTH(AXI_USER_WIDTH)
) axi_slaves[2]();
) axi_slaves[3](); /* modified from 2 to 3 for the AXI IP exercise */
`AXI_ASSIGN(axi_slave_plug, axi_slaves[0])
`AXI_ASSIGN(axi_to_axi_lite_bridge, axi_slaves[1])
`AXI_ASSIGN(wide_alu_slave, axi_slaves[2]) /* modified for AXI IP exercise */

//Interconnect instantiation
soc_interconnect #(
Expand All @@ -188,10 +196,11 @@ module soc_interconnect_wrap
.NR_ADDR_RULES_L2_DEMUX(NR_RULES_L2_DEMUX),
.NR_SLAVE_PORTS_INTERLEAVED(NR_L2_PORTS), // Number of interleaved memory banks
.NR_ADDR_RULES_SLAVE_PORTS_INTLVD(NR_RULES_INTERLEAVED_REGION),
.NR_SLAVE_PORTS_CONTIG(3), // Bootrom + number of private memory banks (normally 1 for
.NR_SLAVE_PORTS_CONTIG(4), // Bootrom + number of private memory banks (normally 1 for
// programm instructions and 1 for programm stack )
// also 1 for exercise memory
.NR_ADDR_RULES_SLAVE_PORTS_CONTIG(NR_RULES_CONTIG_CROSSBAR),
.NR_AXI_SLAVE_PORTS(2), // 1 for AXI to cluster, 1 for SoC peripherals (converted to APB)
.NR_AXI_SLAVE_PORTS(3), // 1 for AXI to cluster, 1 for SoC peripherals (converted to APB), 1 for AXI IP (exercise)
.NR_ADDR_RULES_AXI_SLAVE_PORTS(NR_RULES_AXI_CROSSBAR),
.AXI_MASTER_ID_WIDTH(1), //Doesn't need to be changed. All axi masters in the current
//interconnect come from a TCDM protocol converter and thus do not have and AXI ID.
Expand All @@ -208,8 +217,8 @@ module soc_interconnect_wrap
.interleaved_slaves(l2_interleaved_slaves),
.addr_space_contiguous(CONTIGUOUS_CROSSBAR_RULES),
.contiguous_slaves(contiguous_slaves),
.addr_space_axi(AXI_CROSSBAR_RULES),
.axi_slaves(axi_slaves)
.addr_space_axi(AXI_CROSSBAR_RULES), /* when adding new AXI IP we look for AXI rules */
.axi_slaves(axi_slaves) /* and add axi slave */
);


Expand Down