Post route antenna fix

docker-compose.yml

@@ -7,7 +7,7 @@
 
 services:
   pulp-docker:
-    image: hpretl/iic-osic-tools:2025.07.pre1
+    image: hpretl/iic-osic-tools:2025.11
     environment:
       - UID=${UID}
       - GID=${GID}

openroad/scripts/chip.tcl

@@ -25,6 +25,8 @@ source scripts/init_tech.tcl
 
 set log_id 0
 
+# Set number of threads for multithreaded operations
+set_thread_count 8
 
 ###############################################################################
 # Initialization                                                              #
@@ -48,20 +50,6 @@ report_checks -unconstrained -format end -no_line_splits >> ${report_dir}/${log_
 report_checks -format end -no_line_splits                >> ${report_dir}/${log_id_str}_${proj_name}_checks.rpt
 report_checks -format end -no_line_splits                >> ${report_dir}/${log_id_str}_${proj_name}_checks.rpt
 
-# Size of the chip
-set chipW            1760.0
-set chipH            1760.0
-
-# thickness of annular ring for pads (length of a pad)
-set padRing           180.0
-set coreMargin [expr $padRing + 35]; # space for power ring
-
-utl::report "Initialize Chip"
-initialize_floorplan -die_area "0 0 $chipW $chipH" \
-                     -core_area "$coreMargin $coreMargin [expr $chipW-$coreMargin] [expr $chipH-$coreMargin]" \
-                     -site "CoreSite"
-
-
 utl::report "Connect global nets (power)"
 source scripts/power_connect.tcl
 
@@ -115,13 +103,11 @@ utl::report "###################################################################
 utl::report "# Step ${log_id_str}: GLOBAL PLACEMENT"
 utl::report "###############################################################################"
 
-set_thread_count 8
-
-set GPL_ARGS {  -density 0.60 }
+set GPL_ARGS {  -density 0.75 }
 
-set GPL2_ARGS { -density 0.60
+set GPL2_ARGS { -density 0.75
                 -routability_driven
-                -routability_check_overflow 0.30
+                -routability_check_overflow 0.35
                 -timing_driven }
 # density:            In every part of the chip, about N% of the area is occupied by standard cells
 # routability_driven: Reduce density target when there are a lot of wires in an area
@@ -302,27 +288,26 @@ utl::report "###################################################################
 utl::report "# Step ${log_id_str}: DETAILED ROUTE"
 utl::report "###############################################################################"
 
+utl::report "Detailed route"
+
 # Requires LEF cell with class 'CORE ANTENNACELL', otherwise you need to give a cell
 repair_antennas -ratio_margin 30 -iterations 5
-# check_antennas
 
-utl::report "Detailed route"
-set_thread_count 8
 detailed_route -output_drc ${report_dir}/${log_id_str}_${proj_name}_route_drc.rpt \
-               -bottom_routing_layer Metal2 \
-               -top_routing_layer TopMetal1 \
-               -droute_end_iter 30 \
-               -drc_report_iter_step 5 \
-               -save_guide_updates \
-               -clean_patches \
-               -verbose 1
+            -droute_end_iter 30 \
+            -drc_report_iter_step 5 \
+            -save_guide_updates \
+            -clean_patches \
+            -verbose 1
+
+# Post-route antenna fixing
+source scripts/post_route_antenna_fix.tcl
 
 utl::report "Saving detailed route"
 save_checkpoint ${log_id_str}_${proj_name}.drt
 report_metrics "${log_id_str}_${proj_name}.drt"
 report_image "${log_id_str}_${proj_name}.drt" true false false true
 
-
 ###############################################################################
 # FINISHING                                                                   #
 ###############################################################################

openroad/scripts/floorplan.tcl

@@ -26,6 +26,35 @@ foreach inst $insts {
   }
 }
 
+##########################################################################
+# Die and Core Area 
+##########################################################################
+# Dimensions:                          [um]
+#   final chip size (4sqmm) 2000.0 x 2000.0
+#   io cell depth            180.0 ,  180.0
+#   bonding pad               70.0 ,   70.0
+#   seal ring thickness       35.0 ,   35.0
+#   ---------------------------------------
+#   -> OR core area         1715.0 x 1715.0
+
+set chipH    2000; # final chip height (top to bottom)
+set chipW    2000; # final chip width (left to right)
+set padD      180; # pad depth (edge to core)
+set padW       80; # pad width (beachfront)
+set padBond    70; # bonding pad size
+set sealRing   35; # seal ring thickness
+set powerRing  50; # power ring thickness
+
+# starting from the outside and working towards the core area
+set coreMargin [expr {$sealRing + $padD + $padBond + $powerRing}];
+
+utl::report "Initialize Chip"
+# coordinates are lower-left x and y, upper-right x and y
+initialize_floorplan -die_area "0 0 $chipW $chipH" \
+                     -core_area "$coreMargin $coreMargin [expr $chipW-$coreMargin] [expr $chipH-$coreMargin]" \
+                     -site "CoreSite"
+
+
 ##########################################################################
 # Pads/IOs 
 ##########################################################################
@@ -92,7 +121,7 @@ placeInstance $bank0_sram0 $X $Y R0
 
 # Bank1
 set X [expr $X]
-set Y [expr $Y - $RamSize256x64_H - 15]
+set Y [expr $Y - $RamSize256x64_H - 20]
 placeInstance $bank1_sram0 $X $Y R0
 
 

openroad/scripts/init_tech.tcl

@@ -79,11 +79,11 @@ set dont_use_cells sg13g2_IOPad*
 
 proc makeTracks {} {
     utl::report "Metal Tracks"
-	make_tracks Metal1    -x_offset 0 -x_pitch 0.48 -y_offset 0 -y_pitch 0.48
-	make_tracks Metal2    -x_offset 0 -x_pitch 0.42 -y_offset 0 -y_pitch 0.42
-	make_tracks Metal3    -x_offset 0 -x_pitch 0.48 -y_offset 0 -y_pitch 0.48
-	make_tracks Metal4    -x_offset 0 -x_pitch 0.42 -y_offset 0 -y_pitch 0.42
-	make_tracks Metal5    -x_offset 0 -x_pitch 0.48 -y_offset 0 -y_pitch 0.48
-	make_tracks TopMetal1 -x_offset 1.46 -x_pitch 2.28 -y_offset 1.46 -y_pitch 2.28
+	make_tracks Metal1    -x_offset 0 -x_pitch 0.42 -y_offset 0 -y_pitch 0.42
+	make_tracks Metal2    -x_offset 0 -x_pitch 0.48 -y_offset 0 -y_pitch 0.48
+	make_tracks Metal3    -x_offset 0 -x_pitch 0.42 -y_offset 0 -y_pitch 0.42
+	make_tracks Metal4    -x_offset 0 -x_pitch 0.48 -y_offset 0 -y_pitch 0.48
+	make_tracks Metal5    -x_offset 0 -x_pitch 0.42 -y_offset 0 -y_pitch 0.42
+	make_tracks TopMetal1 -x_offset 1.64 -x_pitch 2.28 -y_offset 1.64 -y_pitch 2.28
 	make_tracks TopMetal2 -x_offset 2.00 -x_pitch 4.00 -y_offset 2.00 -y_pitch 4.00
 }

openroad/scripts/post_route_antenna_fix.tcl

@@ -0,0 +1,153 @@
+# Copyright 2025 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+# Authors:
+# - Tobias Senti      <tsenti@ethz.ch>
+
+## Post-Route Antenna Fix Script
+# This script checks for antenna violations after detailed routing
+# and attempts to fix them by adding antenna diodes to the affected pins.
+# Runs up to $max_iterations or until no violations are found anymore.
+
+# Maximum number of iterations until giving up
+set max_iterations 3
+
+# Counter for unique diode names
+if {![info exists ::antennacounter]} {
+    set ::antennacounter 0
+}
+
+set early_exit 0
+for {set iteration 1} {$iteration <= $max_iterations} {incr iteration} {
+    puts "\n\n=== Antenna Fix Iteration $iteration ==="
+    set report_file_name "post_route_antenna_$iteration.rpt"
+
+    puts "Check for antenna violations"
+    check_antennas -report_file $report_dir/$report_file_name
+
+    puts "Parsing antenna report"
+
+    # Read in report
+    set fp [open $report_dir/$report_file_name]
+    set lines [split [read $fp] "\n"]
+    close $fp
+
+    # Parse report
+    set net_name ""
+    set pin_name ""
+    set has_violation 0
+    set pin_with_violations {}
+    foreach line $lines {
+        # Trim and split line
+        set line [string trim $line]
+        set split_parts [split $line]
+        set parts {}
+        foreach part $split_parts {
+            if { $part ne "" } {
+                lappend parts $part
+            }
+        }
+
+        # Check if it is a net or pin
+        set first_word [lindex $parts 0]
+        if { $first_word eq "Net:" } {
+            set net_name [lindex $parts 1]
+            puts "Processing net: $net_name"
+        }
+        if { $first_word eq "Pin:" } {
+            set pin_name [lindex $parts 1]
+            set has_violation 0
+            puts "  Pin: $pin_name"
+        }
+
+        # Prevent multiple additions of the same pin
+        if { $has_violation eq 0 } {
+            # Check if it is a violation line
+            set last_word [lindex $parts end]
+            if { $last_word eq "(VIOLATED)" } {
+                lappend pin_with_violations $pin_name
+                set has_violation 1
+                puts "    Adding pin $pin_name to violation list"
+            }
+        }
+    }
+
+    puts "\n\n"
+
+    # If no violations, exit loop
+    if { [llength $pin_with_violations] eq 0 } {
+        puts "No antenna violations detected, exiting."
+        set early_exit 1
+        break
+    }
+
+    # Add one antenna diode per pin with violation
+    puts "Add antenna diodes"
+    set block [ord::get_db_block]
+    set ant_master [odb::dbDatabase_findMaster [ord::get_db] "sg13g2_antennanp"]
+    set violation_nets {}
+    foreach pin $pin_with_violations {
+        puts "Pin with antenna violation: $pin"
+        set parts [split $pin "/"]
+        set pin_name [lindex $parts end]
+        set cell_name [join [lrange $parts 0 end-1] "/"]
+
+        # Get instance
+        set inst [odb::dbBlock_findInst $block $cell_name]
+        puts [odb::dbInst_getName $inst]
+
+        # Get iterm (db representation of pin)
+        set iterm [odb::dbInst_findITerm $inst $pin_name]
+
+        # Get net connected to iterm
+        set net [odb::dbITerm_getNet $iterm]
+        set net_name [odb::dbNet_getName $net]
+        # remove backslashes from net name
+        set net_name [string map {"\\" ""} $net_name]
+        lappend violation_nets $net_name
+
+        # Remove routing of the net if it has any
+        set wire [odb::dbNet_getWire $net]
+        if { $wire ne "NULL"} {
+            odb::dbWire_destroy $wire
+        }
+
+        # Create antenna diode instance
+        set ant_name "post_route_ant_diode_[incr ::antennacounter]"
+        set inst [odb::dbInst_create $block $ant_master $ant_name]
+
+        # Connect antenna diode to the net
+        set inst_iterm [odb::dbInst_findITerm $inst "A"]
+        odb::dbITerm_connect $inst_iterm $net
+
+        # Place antenna diode near the pin (gate to protect)
+        set xy [odb::dbITerm_getAvgXY $iterm]
+        puts "Placing antenna diode at $xy"
+        odb::dbInst_setLocation $inst [lindex $xy 1] [lindex $xy 2]
+        odb::dbInst_setPlacementStatus $inst "PLACED"
+    }
+
+    # Refine placement of diodes
+    puts "Detailed placement"
+    detailed_placement
+
+    # Ensure diodes are connected to power
+    puts "Connect power"
+    global_connect
+
+    # Reroute affected nets
+    puts "Detailed route"
+    detailed_route -output_drc ${report_dir}/${log_id_str}_${proj_name}_post_route_antenna_fix_drc.rpt \
+            -droute_end_iter 30 \
+            -drc_report_iter_step 5 \
+            -save_guide_updates \
+            -clean_patches \
+            -verbose 1
+}
+
+# Final antenna check if we have not exited early i.e. fixed all violations
+if {$early_exit eq 0} {
+    puts "Final antenna check"
+    check_antennas -report_file $report_dir/$report_file_name
+}