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7 changes: 3 additions & 4 deletions rtl/clint/clint.sv
Original file line number Diff line number Diff line change
Expand Up @@ -84,16 +84,15 @@ module clint #(
if (obi_req_i.req) begin

if (obi_req_i.a.we) begin : write
automatic logic [31:0] wdata_masked = obi_req_i.a.wdata & be_mask;
unique case ({obi_req_i.a.addr[IntAddrWidth-1:2], 2'b00})
CLINT_MSIP_OFFSET: begin
msip_d = (msip_q & ~be_mask[0]) | wdata_masked[0];
msip_d = (msip_q & ~be_mask[0]) | (obi_req_i.a.wdata[0] & be_mask[0]);
end
CLINT_MTIMECMP_LOW0_OFFSET: begin
mtimecmp_d[31:0] = (mtimecmp_q[31:0] & ~be_mask) | wdata_masked;
mtimecmp_d[31:0] = (mtimecmp_q[31:0] & ~be_mask) | (obi_req_i.a.wdata & be_mask);
end
CLINT_MTIMECMP_HIGH0_OFFSET: begin
mtimecmp_d[63:32] = (mtimecmp_q[63:32] & ~be_mask) | wdata_masked;
mtimecmp_d[63:32] = (mtimecmp_q[63:32] & ~be_mask) | (obi_req_i.a.wdata & be_mask);
end
default: begin
err_d = 1'b1;
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3 changes: 2 additions & 1 deletion rtl/croc_domain.sv
Original file line number Diff line number Diff line change
Expand Up @@ -231,7 +231,8 @@ module croc_domain import croc_pkg::*; #(
datasize: dm::DataCount,
dataaddr: dm::DataAddr
};
dm::hartinfo_t hartinfo = HARTINFO;
dm::hartinfo_t [0:0] hartinfo;
assign hartinfo[0] = HARTINFO;

logic dmi_rst_n, dmi_req_valid, dmi_req_ready, dmi_resp_valid, dmi_resp_ready;
dm::dmi_req_t dmi_req;
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13 changes: 6 additions & 7 deletions rtl/obi_timer/obi_timer.sv
Original file line number Diff line number Diff line change
Expand Up @@ -85,24 +85,23 @@ module obi_timer #(
if (obi_req_i.req) begin

if (obi_req_i.a.we) begin : write
automatic logic [31:0] wdata_masked = obi_req_i.a.wdata & be_mask;
unique case ({obi_req_i.a.addr[IntAddrWidth-1:2], 2'b00})
OBI_TIMER_COUNT_OFFSET: begin
count_d = (count_q & ~be_mask) | wdata_masked;
count_d = (count_q & ~be_mask) | (obi_req_i.a.wdata & be_mask);
end
OBI_TIMER_COMPARE_OFFSET: begin
compare_d = (compare_q & ~be_mask) | wdata_masked;
compare_d = (compare_q & ~be_mask) | (obi_req_i.a.wdata & be_mask);
count_d = '0;
end
OBI_TIMER_CTRL_OFFSET: begin
enable_d = (enable_q & ~be_mask[0]) | wdata_masked[0];
autoreset_d = (autoreset_q & ~be_mask[1]) | wdata_masked[1];
enable_d = (enable_q & ~be_mask[0]) | (obi_req_i.a.wdata[0] & be_mask[0]);
autoreset_d = (autoreset_q & ~be_mask[1]) | (obi_req_i.a.wdata[1] & be_mask[1]);
end
OBI_TIMER_STATUS_OFFSET: begin
if (wdata_masked[0]) begin
if (obi_req_i.a.wdata[0] & be_mask[0]) begin
expired_sticky_d = 1'b0;
end
if (wdata_masked[1]) begin
if (obi_req_i.a.wdata[1] & be_mask[1]) begin
overflow_sticky_d = 1'b0;
end
end
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11 changes: 5 additions & 6 deletions rtl/soc_ctrl/soc_ctrl_regs.sv
Original file line number Diff line number Diff line change
Expand Up @@ -69,22 +69,21 @@ module soc_ctrl_regs #(
if (obi_req_i.req) begin

if (obi_req_i.a.we) begin : write
automatic logic [31:0] wdata = obi_req_i.a.wdata & be_mask;
unique case ({obi_req_i.a.addr[IntAddrWidth-1:2], 2'b00})
SOC_CTRL_BOOTADDR_OFFSET: begin
boot_addr_d = wdata;
boot_addr_d = obi_req_i.a.wdata & be_mask;
end
SOC_CTRL_FETCHEN_OFFSET: begin
fetch_en_d = wdata[0];
fetch_en_d = obi_req_i.a.wdata[0] & be_mask[0];
end
SOC_CTRL_CORESTATUS_OFFSET: begin
core_status_d = wdata;
core_status_d = obi_req_i.a.wdata & be_mask;
end
SOC_CTRL_BOOTMODE_OFFSET: begin
boot_mode_d = wdata[0];
boot_mode_d = obi_req_i.a.wdata[0] & be_mask[0];
end
SOC_CTRL_SRAM_DLY_OFFSET: begin
sram_dly_d = wdata[0];
sram_dly_d = obi_req_i.a.wdata[0] & be_mask[0];
end
default: begin
err_d = 1'b1;
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2 changes: 1 addition & 1 deletion rtl/user_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ package user_pkg;
localparam bit [31:0] UserRomAddrOffset = croc_pkg::UserBaseAddr; // 32'h2000_0000;
localparam bit [31:0] UserRomAddrRange = 32'h0000_1000; // every subordinate has at least 4KB

localparam int unsigned NumDemuxSbrRules = NumUserDomainSubordinates; // number of address rules in the decoder
localparam int unsigned NumDemuxSbrRules = (NumUserDomainSubordinates > 0) ? NumUserDomainSubordinates : 1; // number of address rules in the decoder
localparam int unsigned NumDemuxSbr = NumDemuxSbrRules + 1; // additional OBI error, used for signal arrays

// Enum for bus indices
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