Fix Snitch Cache Configuration, Update Memory Map, and Improve Simulation Support

[Xeratec]

This pull request updates the Chimera SoC to fix the instruction cache configuration of the Snitch cluster, increase the memory island size, remap the HyperBus, and enable aliasing in the L1 TCDM of the Snitch clusters. Additionally, it provides support for a fast virtual UART in RTL simulations, introduces a useful waveform configuration, and synchronizes the cluster clock with the SoC clock in the test bench. Finally, I added some helpful comments to enhance the understanding of the configuration values.

Memory Island Size

• In the current configuration, each cluster has 128 KiB of L1 TCDM
• Hence, I argue a larger L2 of 512 KiB makes much more sense.

HyperBus Address

• So far, we have mapped the HyperBus at 0x5000_0000; however, we usually use 0x8000_0000 for the DRAM.
• Hence, I remapped the HyperBus to 0x8000_0000.

HyperBus Configuration

• So far, the IsClockODelayed parameter in the HyperBus wrapper was set to zero, resulting in no delay line in the TX path; however, this can be problematic at higher frequencies.
• Hence, I enabled the configurable delay for the TX path.

Snitch Cluster Instruction Cache Configuration

• The default PMA (Physical Memory Attributes) configuration is zero.
• Hence, I added logic to correctly cache the memory island and memory-mapped HyperBus.

Snitch Cluster TCDM Aliasing

• So far, TCDM aliasing was disabled in the Snitch cluster; however, this is a useful feature in a multi-cluster context to load data from L2 into L1 for all clusters.
• Hence, I enabled L1 TCDM aliasing at 0x1800_0000 by default.