pulp-platform · DiyouS · Apr 15, 2026 · Apr 16, 2026 · May 4, 2026 · May 4, 2026
diff --git a/.gitignore b/.gitignore
@@ -32,3 +32,9 @@ hardware/deps/*
 *.tdb
 util/lint/sg_projects
 util/lint/tmp
+hardware/bootrom/bootdata.cc
+hardware/bootrom/bootdata_bootrom.cc
+hardware/bootrom/bootrom.bin
+hardware/bootrom/bootrom.dump
+hardware/bootrom/bootrom.elf
+hardware/bootrom/bootrom.sv
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -8,29 +8,32 @@ variables:
   GIT_SUBMODULE_STRATEGY: none
   ROOT_DIR: '$CI_PROJECT_DIR'
   APPS: "tests"
-  PATH: '/home/gitlabci/.cargo/bin:/usr/local/bin:/usr/bin:/usr/sbin:/sbin:/usr/local/condor/bin:/usr/sepp/bin:$CI_PROJECT_DIR/install/verilator/bin:/home/gitlabci/.local/bin'
+  PATH: '$HOME/.cargo/bin:/usr/local/bin:/usr/bin:/usr/sbin:/sbin:/usr/local/condor/bin:/usr/sepp/bin:$CI_PROJECT_DIR/install/verilator/bin:$HOME/.local/bin'
   OBJCACHE: ''
   CC:  '/usr/pack/gcc-11.2.0-af/linux-x64/bin/gcc'
   CXX: '/usr/pack/gcc-11.2.0-af/linux-x64/bin/g++'
   CMAKE: 'cmake-3.28.3'
   python: 'python3'
   python3: 'python3'
+  # Config to build and test
+  CI_CONFIG: 'cachepool_fpu_2g'
+  SW_PREFIX: 'test-cachepool-'
 
 default:
-  tags: [dolent]
+  tags: [shared]
 
 stages:
   - build
+  - test
 
-.base:
-  artifacts:
-    when: always
-    expire_in: 1 day
-
-build-vsim:
-  extends: .base
+# ---------------------------------------------------------------------------
+# Build stage: compile RTL and software for CI_CONFIG.
+# Parallel jobs within the same pipeline share $HOME, so the toolchain
+# installed by make quick-tool is automatically available to all test jobs.
+# ---------------------------------------------------------------------------
+build:
   stage: build
-  timeout: 5h
+  timeout: 4h 30m
   script:
     - echo "Using CC=$CC"
     - echo "Using CXX=$CXX"
@@ -39,10 +42,57 @@ build-vsim:
     - make quick-tool
     - make init
     - make dram-build
-    - cd util/auto-benchmark
-    - chmod +x ./run_ci.sh
-    - ./run_ci.sh
+    - python3 -m pip install --quiet -r requirements.txt
+    - make clean generate vsim config=$CI_CONFIG
+  artifacts:
+    when: always
+    expire_in: 1 day
+    paths:
+      # QuestaSim compiled work library
+      - sim/work/
+      # vsim wrapper scripts (exclude sim/bin/logs/ — not needed by test jobs)
+      - sim/bin/cachepool_cluster.vsim
+      - sim/bin/cachepool_cluster.vsim.gui
+      # DPI shared library
+      - sim/work-dpi/
+      # Software binaries for all kernels
+      - software/build/CachePoolTests/
+      # DRAMSys shared libraries and config files (referenced by vsim at runtime)
+      - hardware/deps/dram_rtl_sim/dramsys_lib/DRAMSys/build/lib/
+      - hardware/deps/dram_rtl_sim/dramsys_lib/DRAMSys/configs/
 
+# ---------------------------------------------------------------------------
+# Test stage: run each kernel in parallel on a separate runner.
+# Each job downloads the build artifacts, runs one simulation, and checks
+# the output log for failures.
+# ---------------------------------------------------------------------------
+test:
+  stage: test
+  timeout: 1h
+  needs: [build]
+  parallel:
+    matrix:
+      - KERNEL:
+          - spin-lock
+          - load-store_M16
+          - fdotp-32b_M32768
+          - gemv_M512_N128_K32
+          - fmatmul-32b_M64_N64_K64
+          - fft-32b_M1024_N16
+          - multi_producer_single_consumer_double_linked_list_M1_N1350_K10
+          - byte-enable
+  script:
+    # The vsim script writes a .rtlbinary marker here; ensure the dir exists.
+    - mkdir -p sim/bin/logs
+    - chmod +x sim/bin/cachepool_cluster.vsim
+    - BIN="${SW_PREFIX}${KERNEL}"
+    - sim/bin/cachepool_cluster.vsim software/build/CachePoolTests/$BIN 2>&1 | tee test_${KERNEL}.log
+    - python3 util/auto-benchmark/check-ci.py test_${KERNEL}.log
   artifacts:
+    when: always
+    expire_in: 1 day
     paths:
-      - util/auto-benchmark/logs
+      # Full simulation log
+      - test_*.log
+      # Performance-monitor trace files written by the simulator
+      - sim/bin/logs/
diff --git a/Bender.lock b/Bender.lock
@@ -16,17 +16,34 @@ packages:
     - common_verification
     - tech_cells_generic
   axi_riscv_atomics:
-    revision: 97dcb14ef057cbe5bd70dda2060b5bb9e7e04c6d
-    version: 0.7.0
+    revision: 97a1dd2ac643c276880420a0cf8eea697f228aa9
+    version: 0.8.3
     source:
       Git: https://github.com/pulp-platform/axi_riscv_atomics.git
     dependencies:
     - axi
     - common_cells
     - common_verification
+  axi_stream:
+    revision: 54891ff40455ca94a37641b9da4604647878cc07
+    version: 0.1.1
+    source:
+      Git: https://github.com/pulp-platform/axi_stream.git
+    dependencies:
+    - common_cells
+  cluster_icache:
+    revision: ce0ed94a5b95f5c76b9fa51940303fcce53f56e5
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/cluster_icache.git
+    dependencies:
+    - axi
+    - common_cells
+    - scm
+    - tech_cells_generic
   common_cells:
-    revision: 9afda9abb565971649c2aa0985639c096f351171
-    version: 1.38.0
+    revision: 9ca8a7655f741e7dd5736669a20a301325194c28
+    version: 1.39.0
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
@@ -45,8 +62,27 @@ packages:
       Git: https://github.com/pulp-platform/dram_rtl_sim.git
     dependencies:
     - axi
+  floo_noc:
+    revision: 97306733f33acbb646c7e403c03a674fc1404b44
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/FlooNoC.git
+    dependencies:
+    - axi
+    - axi_riscv_atomics
+    - common_cells
+    - common_verification
+    - floo_noc_pd
+    - fpnew
+    - idma
+  floo_noc_pd:
+    revision: null
+    version: null
+    source:
+      Path: hardware/deps/floo_noc/./pd
+    dependencies: []
   fpnew:
-    revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315
+    revision: e5aa6a01b5bbe1675c3aa8872e1203413ded83d1
     version: null
     source:
       Git: https://github.com/pulp-platform/cvfpu.git
@@ -61,14 +97,16 @@ packages:
     dependencies:
     - common_cells
   idma:
-    revision: b31e8f019c657eff4126bc789f0336d403da6766
-    version: 0.4.2
+    revision: 28a36e5e07705549e59fc33db96ab681bc1ca88e
+    version: 0.6.5
     source:
       Git: https://github.com/pulp-platform/iDMA.git
     dependencies:
     - axi
+    - axi_stream
     - common_cells
     - common_verification
+    - obi
     - register_interface
   insitu-cache:
     revision: fa761ddebc946f9b46509d84945bf41ee1a9ec49
@@ -79,6 +117,14 @@ packages:
     - axi
     - common_cells
     - register_interface
+  obi:
+    revision: 0155fc34e900c7c884e081c0a1114a247937ff69
+    version: 0.1.7
+    source:
+      Git: https://github.com/pulp-platform/obi.git
+    dependencies:
+    - common_cells
+    - common_verification
   register_interface:
     revision: 146501d80052b61475cdc333d3aab4cd769fd5dc
     version: 0.3.9
@@ -96,6 +142,13 @@ packages:
     dependencies:
     - common_cells
     - tech_cells_generic
+  scm:
+    revision: 1976c7efb4979271eee2abe262fde0f9a20e2557
+    version: 1.2.1
+    source:
+      Git: https://github.com/pulp-platform/scm.git
+    dependencies:
+    - tech_cells_generic
   spatz:
     revision: ed25c78dd72d839db8141287f9516d78ee399b93
     version: null

diff --git a/Bender.yml b/Bender.yml
@@ -10,13 +10,14 @@ dependencies:
   axi_riscv_atomics:   { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",  version: 0.7.0                }
   common_cells:        { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.28.0               }
   FPnew:               { git: "https://github.com/pulp-platform/cvfpu.git",              rev:     pulp-v0.1.3          }
-  idma:                { git: "https://github.com/pulp-platform/iDMA.git",               version: 0.4.2                }
   register_interface:  { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8                }
   riscv-dbg:           { git: "https://github.com/pulp-platform/riscv-dbg.git",          version: 0.7.0                }
   tech_cells_generic:  { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11               }
   Insitu-Cache:        { git: "https://github.com/pulp-platform/Insitu-Cache.git",       rev:     zexin/cachepool_dev  }
-  spatz:               { git: "https://github.com/pulp-platform/spatz.git",              rev:     cachepool-32b        }
   dram_rtl_sim:        { git: "https://github.com/pulp-platform/dram_rtl_sim.git",       rev:     cachepool            }
+  floo_noc:            { git: "https://github.com/pulp-platform/FlooNoC.git",            rev:     main                 }
+  cluster_icache:      { git: "https://github.com/pulp-platform/cluster_icache.git",     rev:     main                 }
+  spatz:               { git: "https://github.com/pulp-platform/spatz.git",              rev:     cachepool-32b        }
 
 workspace:
   checkout_dir: "./hardware/deps"
@@ -29,22 +30,27 @@ sources:
   - hardware/src/tcdm_cache_interco.sv
   - hardware/src/tcdm_id_remapper.sv
   - hardware/src/spatz_cache_amo.sv
+  # FlooNoC
+  - hardware/generated/floo_cachepool_noc_pkg.sv
   # Memory-mapped register
   - hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv
   - hardware/cachepool_peripheral/cachepool_peripheral_reg_top.sv
   - hardware/cachepool_peripheral/cachepool_peripheral.sv
   # Bootrom
   - hardware/bootrom/bootrom.sv
-  # Barrier
-  - hardware/src/cachepool_tile_barrier.sv
-  - hardware/src/cachepool_cluster_barrier.sv
   # Level 1
   - hardware/src/cachepool_pkg.sv
   - hardware/src/cachepool_cc.sv
+  # Barrier
+  - hardware/src/cachepool_tile_barrier.sv
+  - hardware/src/cachepool_cluster_barrier.sv
+  # ICache
+  - hardware/src/axi_hier_interco.sv
   # Level 2
   - hardware/src/cachepool_tile.sv
   # Level 3
   - hardware/src/cachepool_group.sv
+  - hardware/src/cachepool_group_noc_wrapper.sv
 
   - hardware/src/cachepool_cluster.sv
   # Level 4

diff --git a/Makefile b/Makefile
@@ -67,7 +67,7 @@ CACHE_PATH            := $(shell [ -x "$(BENDER)" ] && $(BENDER) path insitu-cac
 
 # Configurations
 CFG_DIR               ?= ${CACHEPOOL_DIR}/config
-config                ?= cachepool_512
+config                ?= cachepool_fpu_2g
 
 # Compiler choice for SW cmake
 COMPILER              ?= llvm
@@ -163,6 +163,30 @@ $(BOOTROM_DIR)/bootrom.sv: $(BOOTROM_DIR)/bootrom.bin $(BOOTROM_DIR)/bootdata.cc
 	${PYTHON} $(SCRIPTS_DIR)/generate_bootrom.py \
 		$< -c $(HJSON_OUT) --output $@
 
+###########
+# FlooNoC #
+###########
+FLOO_DIR      ?= $(shell $(BENDER_INSTALL_DIR)/bender path floo_noc)
+FLOO_GEN_OUTDIR ?= $(ROOT_DIR)/hardware/generated
+FLOO_CFG      ?= $(ROOT_DIR)/config/floonoc_cachepool_4g.yml
+FLOO_NAME     = cachepool
+FLOO_NOC      ?= $(FLOO_GEN_OUTDIR)/floo_$(FLOO_NAME)_noc_pkg.sv
+
+$(info FLOO_DIR: $(FLOO_DIR))
+
+# Generates the sources for FlooNoC
+.PHONY: update-floonoc install-floogen clean-floonoc
+install-floogen:
+	pip install -e $(FLOO_DIR) --quiet
+
+update-floonoc: $(FLOO_NOC)
+$(FLOO_NOC): install-floogen $(FLOO_CFG)
+	mkdir -p $(FLOO_GEN_OUTDIR)
+	PATH="$(HOME)/.local/bin:$(PATH)" floogen pkg -c $(FLOO_CFG) -o $(FLOO_GEN_OUTDIR) --no-format
+
+clean-floonoc:
+	rm -f $(FLOO_NOC)
+
 ###########
 # DramSys #
 ###########
@@ -232,33 +256,32 @@ VLOG_FLAGS += -64
 VLOG_DEFS = -DCACHEPOOL
 
 # Cluster configuration
+VLOG_DEFS += -DNUM_GROUPS=$(num_groups)
+VLOG_DEFS += -DNUM_GROUPS_X=$(num_groups_x)
 VLOG_DEFS += -DNUM_TILES=$(num_tiles)
 VLOG_DEFS += -DNUM_CORES=$(num_cores)
 VLOG_DEFS += -DDATA_WIDTH=$(data_width)
 VLOG_DEFS += -DADDR_WIDTH=$(addr_width)
 
 # Tile configuration
-VLOG_DEFS += -DNUM_CORES_PER_TILE=$(num_cores_per_tile)
 VLOG_DEFS += -DREFILL_DATA_WIDTH=$(refill_data_width)
 
 # L1 Data Cache
 VLOG_DEFS += -DL1D_CACHELINE_WIDTH=$(l1d_cacheline_width)
-VLOG_DEFS += -DL1D_SIZE=$(l1d_size)
-VLOG_DEFS += -DL1D_BANK_FACTOR=$(l1d_bank_factor)
 VLOG_DEFS += -DL1D_COAL_WINDOW=$(l1d_coal_window)
 VLOG_DEFS += -DL1D_NUM_WAY=$(l1d_num_way)
-VLOG_DEFS += -DL1D_TILE_SIZE=$(l1d_tile_size)
 VLOG_DEFS += -DL1D_TAG_DATA_WIDTH=$(l1d_tag_data_width)
 VLOG_DEFS += -DL1D_NUM_BANKS=$(l1d_num_banks)
 VLOG_DEFS += -DL1D_DEPTH=$(l1d_depth)
 
 # CachePool CC / core cluster
-VLOG_DEFS += -DSPATZ_FPU_EN=$(spatz_fpu_en)
 VLOG_DEFS += -DSPATZ_NUM_FPU=$(spatz_num_fpu)
 VLOG_DEFS += -DSPATZ_NUM_IPU=$(spatz_num_ipu)
 VLOG_DEFS += -DSPATZ_MAX_TRANS=$(spatz_max_trans)
 VLOG_DEFS += -DSNITCH_MAX_TRANS=$(snitch_max_trans)
 VLOG_DEFS += -DREMOTE_PORT_PER_CORE=$(num_remote_ports_per_tile)
+VLOG_DEFS += -DRG_PORT_PER_CORE=$(num_rg_ports_per_core)
+VLOG_DEFS += -DNOC_PORT_PER_TILE=$(num_noc_ports_per_tile)
 
 # AXI configuration
 VLOG_DEFS += -DAXI_USER_WIDTH=$(axi_user_width)
@@ -268,14 +291,12 @@ VLOG_DEFS += -DL2_CHANNEL=$(l2_channel)
 VLOG_DEFS += -DL2_BANK_WIDTH=$(l2_bank_width)
 VLOG_DEFS += -DL2_INTERLEAVE=$(l2_interleave)
 
-# Peripherals / memory map
-VLOG_DEFS += -DSTACK_ADDR=$(stack_addr)
+# Stack / SPM (boot_addr, stack_addr, periph_start_addr, uart_addr used by hjson
+# generator via environment; not consumed as SV defines)
 VLOG_DEFS += -DSTACK_HW_SIZE=$(stack_hw_size)
 VLOG_DEFS += -DSTACK_HW_DEPTH=$(stack_hw_depth)
 VLOG_DEFS += -DSTACK_TOT_SIZE=$(stack_tot_size)
-VLOG_DEFS += -DPERIPH_START_ADDR=$(periph_start_addr)
-VLOG_DEFS += -DBOOT_ADDR=$(boot_addr)
-VLOG_DEFS += -DUART_ADDR=$(uart_addr)
+VLOG_DEFS += -DSTACK_TOT_DEPTH=$(stack_tot_depth)
 
 ENABLE_CACHEPOOL_TESTS ?= 1
 

diff --git a/config/cachepool.hjson b/config/cachepool.hjson
@@ -53,11 +53,11 @@
       register_offload_rsp: true
     },
 
-    nr_tiles: 4,
+    nr_tiles: 8,
 
-    // Repeat the compute core template N times (driven by 16)
+    // Repeat the compute core template N times (driven by 32)
     cores: [
-      { $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" }
+      { $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" },{ $ref: "#/compute_core_template" }
     ],
 
     icache: {