List Mode Data Format

Introduction

The list mode data format is at minimum 4 words per channel. Options in the Channel CSRA allow the user to output more information on the signal as well as traces. The format of the list mode data is firmware dependent, make sure that you have the proper data format for your specific firmware.

#Firmware Released on 02/02/2016

##Firmware Files This firmware is only compatible with the 12-bit 250 MS/s modules.

• System FPGA File : syspixie16_revfvandle_adc250mhz_r34301.bin
• Signal Processing FPGA File : fippixie16_revfvandle_12b250m_r34302.bin
• DSP Code Files :
  • Pixie16DSP_revfvandle_12b250m_r34300.ldr
  • Pixie16DSP_revfvandle_12b250m_r34300.var
  • Pixie16DSP_revfvandle_12b250m_r34300.lst

Channel CSRA

Header

The header can contain between 4 and 18 words depending on the choices made in the Channel CSRA. At minimum the header will contain the following four words.

Optional Header Words

These header words will follow the first four in order of energy sums/baseline, QDC sums and external timestamps. These header words are controlled from the Channel CSRA by enabling the appropriate bits.

Raw Energy Sums and Baseline

Controlled via Channel CSRA bit 12.

Note : The baseline is stored in an IEEE standard number format. It can be converted to decimal using IEEEFloating2Decimal(unsigned int IEEEFloatingNumber).

QDC sums

Controlled via Channel CSRA bit 9.

External Clock Timestamps

Controlled via Channel CSRA bit 21.

Traces

Traces immediately follow the last word in the header. The ADC values are 12-bit; so, two values are stored into a single 32-bit word.