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@ChucklesOnGitHub ChucklesOnGitHub commented Dec 5, 2025

addresses #120

@ChucklesOnGitHub ChucklesOnGitHub marked this pull request as draft December 5, 2025 14:01
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Actually, specififying this at the level of the breakout board is not correct.
The PCIe controller clock port implementation is what needs to be specified:

image

However, it might be useful to constrain this in the documentation and ask users to connect the breakout board and the controller in a fixed way such as Clk0 - In0, Clk1 - In1, Clk2 - O1.

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cjsha commented Dec 7, 2025

Actually, specififying this at the level of the breakout board is not correct.

Agreed.

it might be useful to constrain this in the documentation and ask users to connect the breakout board and the controller in a fixed way such as Clk0 - In0, Clk1 - In1, Clk2 - O1.

I think later versions of the bracket for the pcie controller have different labels than the 3D printed version shown in the photo you posted,

image

but I agree regardless that what you suggest here would be helpful for anyone with the older version.

Also update the list of compatible hardware
for breakout board & pcie host
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I made some changes to address your comments and also updated the list of compatible headstages for breakout board & pcie host.

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ChucklesOnGitHub commented Dec 11, 2025

I've made some more edits. Maybe they are a bit of a stretch. But my beef with how things are is that it is hard to understand all the connectivity and capatibilities from a single page/pic. And I understand that the bb is providing access to functionality that is ultimately on the controller, but the user sees the bb.. the controller is tucked away.

I think updating the pics to v1.6 of the bb and the new bracket and updating some labels will help. We're taking the updated pics tomorrow

@cjsha Do you have the editable documents of these pics that have labels?
image
image

@ChucklesOnGitHub ChucklesOnGitHub self-assigned this Dec 11, 2025
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@cjsha is this correct?
image

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cjsha commented Dec 14, 2025

@cjsha is this correct?

I don't know anything about the Harp Clock 1 Input label. I've never used that.

.. note:: There may be more IO present on the breakout board than is available
on a particular host board. For instance, :ref:`pcie_host` has two coaxial
links, but the breakout board provides four. This is is by design. The breakout
links, but the v1.5beta breakout board provides four. This is is by design. The breakout
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do you know what they had in mind for this? I don't foresee future compatible host hardware considering that we got rid of those ports on v1.6. I'm wondering if "This is is by design. The breakout is designed to be compatible with future host hardware." should be totally deleted.

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The 4 ports on the breakout?
The original idea was that that would allow to connect 2 FMC to a single breakout. But of course, that would have been only true for headstages, the A/DIO would have been unconnected. Which would have been even more confusing. That's what we decided that a breakout should match 1:1 the ports on a FMC

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ChucklesOnGitHub commented Dec 15, 2025

@jonnew @aacuevas if either of you could confirm the following, we can merge here:

  • labels on PCIe - would the clock labels be correct?

@cjsha is this correct? image

  • 4x port text description

do you know what they had in mind for this? I don't foresee future compatible host hardware considering that we got rid of those ports on v1.6. I'm wondering if "This is is by design. The breakout is designed to be compatible with future host hardware." should be totally deleted.

  • labels on breakout board. Whilst crossing lines is not the most elegant, adding the specifics of what the clock ports are (input or output, onix or harp) gives an overview of all the in/out functionality available to the user on the breakout board. I've left out the Config because that is for setup, and all the connections to the host which are described elsewhere. An alternative would be to not mention that clcok port 1 is a Harp input, and leave it blank like Clock 0 is. Then in the PCIe card what they are is made explicit.
image
  • cable labels on the side of the breakout board. I really wanted to put the in/out here, because it is useful to reference while connecting. But since this is a property of the PCIe controller, and the labels over there are explicit, I think this is enough. The picture only depicts three cables being plugged in (two headstage ports and the I/O), because those are the most common.
bb_1r6_cables_callouts

Once I know this, I'll clear the repo of old pics, update the names in the text so they are linked properly, and covert this draft PR to a final one.

Thank you!

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@ChucklesOnGitHub the final ones are the last 3 pictures you posted, right? They seem correct.
I would call the clock0 "unused" rather than "disabled", though

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4 participants