eth: A proposal to add Ethernet interface & RGMII transceiver module

[ghost]

On this pull request, I propose a fundamental design for implementing the Ethernet interface and a working RGMII transmitter/receiver module. Here are the main features:

1. eth.Endpoint: A representation of a container for the received/transmitted packet. It is based on MiSoC's stream.Endpoint and LiteEthMini. This Python module can be used and further extended for implementing the MAC interface, such the Preamble and CRC.

2. eth.rgmii.EthRGMII: A RGMII transmitter/receiver module. Separately, EthRGMIITX and EthRGMIIRX are the transmitter and receiver module respectively. Currently, no unit tests were made, but the modules have been tested on a Lattice ECP5, using these two SoC module designs:

   • TX test that sends a packet repeatedly
   • RX test that displays the raw bytes of the whole Ethernet packet on the serial port