Add mcounteren register

[SamuelRiedel]

This PR adds the mcounteren register, which has so far been tied to zero and implements the U-mode performance counter aliases. The mcounteren register can be locked with an external MUBI signal (mcounteren_writable_i).

DV:
This PR adds two directed tests:

• mcounteren_test goes through multiple configurations of the mcounteren register and validates that u-mode can only access the ones enabled.
• mcounteren_lock_test verifies that the mcounteren CSR cannot be modified without the mcounteren_writable_i signal being set.

To Dos:

• For the directed tests and the cosim to pass, we have to update riscv-isa-sim to also support those performance counters: Enable ZIHPM unpriviledged performance counters riscv-isa-sim#29
• Currently, u-mode counter reads will lead to illegal instruction exceptions. However, we are not gating the value at the CSR module's interface for simplicity. The signal will not leave the core, but we should double-check that this is no security issue.