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This refactors instr_vif to use rvfi_id_done instead of instr_new_id to track when a new instruction appears in the ID stage. This interface and signal are only used to keep track of instruction fetch errors by using the aforementioned valid signal and checking whether the rvfi_order_id has advanced. However, instr_new_id will be gated if an instruction fetch error occurs after another error, causing us to overlook the fetch_err in the verification. With this change, we also no longer need to look at valid_id since the rvfi_id_done already contains this information.

This will fix failing riscv_mem_error_test in the nightly runs and the failing CI in #2324

@SamuelRiedel SamuelRiedel marked this pull request as ready for review December 18, 2025 09:32
This refactors `instr_vif` to use `rvfi_id_done` instead of
`instr_new_id` to track when a new instruction appears in the ID stage.
This interface and signal are only used to keep track of instruction
fetch errors by using the aforementioned valid signal and checking
whether the `rvfi_order_id` has changed. However, if an instruction
fetch error is consecutive to another error, `instr_new_id` will be
gated, which leads us to miss the `fetch_err` in the verification.

This will fix failing `riscv_mem_error_test`
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