runsc: serialize RDMA and PCI sysfs data at boot

[atoniolo76]

Snapshot host RDMA/InfiniBand and PCI device sysfs attributes before pivot_root (while the host sysfs is still accessible), serialize them as JSON, and reconstruct them as virtual kernfs entries inside the sentry. This gives NCCL and libibverbs the topology information they need for device discovery and PCI distance computation without granting the sandbox access to the real host sysfs.

Key components:

• pkg/sentry/fsimpl/sys/rdma.go: RDMA device data collection and virtual /sys/class/infiniband{,_verbs}/ + /sys/class/net/ entries
• pkg/sentry/fsimpl/sys/pci_devices.go: PCI topology collection and virtual /sys/devices/pci*/ hierarchy with symlinks for NCCL
• runsc/cmd/chroot.go: collection before pivot_root
• runsc/cmd/boot.go: --rdmaproxy flag and data deserialization
• runsc/boot/vfs.go: wire sysfs InternalData for RDMA/PCI
• runsc/config: --rdmaproxy configuration flag

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[trantoji]

Hey @atoniolo76,

This PR is serializing and virtualizing three things: PCIe topology, NUMA layout, and other RDMA info. Are you open to splitting this PR into three?

What are your thoughts on the following structure:

1. Infra to serialize and virtualize the minimal set of sysfs nodes and gate it (via flag) to get ib_write_cuda_bw to work. (i'm assuming this tool is dumb and does not need NUMA and PCIe topology information, we can simply target a net interface and CUDA device).
2. Serialize and virtualize the PCIe topology and NUMA layout and keep the code vendor agnostic. Applications need the PCIe topology (bridges, NICs, and accelerator locations) so that threads can initiate data flows that take the fast path (PCIe P2P). They need the NUMA layout to optimize execution, i.e pin their control threads to the local CPU socket to avoid copies traversing the CPU socket interconnect.
3. Infra to add vendor specific quirks to the virtualized sysfs to get NCCL and CX device working.

Splitting it this way separates the generic hardware platform from the vendor-specific middleware heuristics.