Enable PREFETCH_L1 for RISC-V to improve performance#4643
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Polaris-911 wants to merge 1 commit intofacebook:devfrom
Open
Enable PREFETCH_L1 for RISC-V to improve performance#4643Polaris-911 wants to merge 1 commit intofacebook:devfrom
Polaris-911 wants to merge 1 commit intofacebook:devfrom
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Description
This PR enables
PREFETCH_L1(match)inzstd_decompress_block.cfor the RISC-V architecture.Similar to AArch64, prefetching the match sequence before copying can bring a slight performance improvement on high-performance RISC-V processors.
Why is it needed?
Currently, this prefetch optimization is only enabled for
__aarch64__. By extending the macro to include__riscv, we can take advantage of hardware data prefetching on RISC-V platforms, resulting in better CPU cache utilization during decompression.Benchmark Results
Tests were performed on a SOPHON SG2044 RISC-V machine using the
silesia.tardataset.Command:
numactl -l -C 12 ./zstd -b1 -e1 ../silesia.tar