fby4: wf: Avoid CXL DIMM polling during Set EID and DIMM init#2725
fby4: wf: Avoid CXL DIMM polling during Set EID and DIMM init#2725Wiwynn-Evan wants to merge 1 commit into
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Summary: # [Issue Description] - YV4T1M-2265 - BMC recorded "CXL DEASSERTED" SEL after conducting SD BIC update with CXL 3.2.2. # [Root Cause] WF may perform CXL Set EID, DIMM present initialization, and DIMM temperature sensor polling at overlapping timing. During these timing windows, CXL may not receive the expected response from WF BIC. Based on the CXL team's previous explanation, when WF BIC does not respond as expected, the Vistara I2C Master may hang indefinitely and eventually trigger the watchdog, resulting in a CXL crash. Since the CXL team believes that improving CXL's I2C timeout handling may impact the underlying I2C driver code, this scenario has been treated as a CXL limitation. # [Solution] - This change is mainly a workaround for the CXL limitation previously raised by the CXL team. - This change can only reduce the failure rate, but cannot fully resolve the CXL limitation. - Added a per-CXL flag while WF is performing Set EID to CXL. - Adjusted the execution timing between DIMM presence checking and sensor polling. - Avoid performing DIMM temperature polling to CXL while the corresponding CXL is under Set EID or DIMM present initialization. - Addressed the reviewdog suggestion.
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This should be a false positive from the static analyzer.
plat_get_dimm_cache() is a weak platform hook in common vistara.c. Although the common weak default implementation does not return a negative value, this function is overridden by the yv4-wf platform implementation. In yv4-wf, the platform implementation may return a negative value when the DIMM temperature cache is invalid or the cached read fails. Therefore, f_val < 0 is not always false in the actual yv4-wf build. It is used to detect an invalid cached DIMM temperature and return SENSOR_FAIL_TO_ACCESS. To avoid changing the existing platform cache behavior only for this static analysis warning, I prefer to keep the current logic unchanged. |
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[Issue Description]
[Root Cause]
WF may perform CXL Set EID, DIMM present initialization, and DIMM temperature sensor polling at overlapping timing. During these timing windows, CXL may not receive the expected response from WF BIC. Based on the CXL team's previous explanation, when WF BIC does not respond as expected, the Vistara I2C Master may hang indefinitely and eventually trigger the watchdog, resulting in a CXL crash. Since the CXL team believes that improving CXL's I2C timeout handling may impact the underlying I2C driver code, this scenario has been treated as a CXL limitation.
[Solution]