Add tests for MachRegister::getBaseRegister

[hainest]

The x86 tests won't pass until dyninst/dyninst#1851 is merged.

@bbiiggppiigg The amd gpu checks seem to be no-ops since it just stuffs the ID into s0, but that's the same as adding the ID to 0. For example,

s10 & 0x000000ff -> 0x0000000a
s0 -> 0x94010b00
s10 & 0x000000ff | s0 -> 0x94010b0a -> s10

Should it be mapping s<N> to s0?

[kupsch]

I think it be worth add a couple of more checks for x86 and x86_64, otherwise looks good (the suggested changes are untested).

I would think the AMD scalar and vector registers should be their own base register, so that is likely a bug unless @bbiiggppiigg says otherwise.

[bbiiggppiigg]

The x86 tests won't pass until dyninst/dyninst#1851 is merged.

@bbiiggppiigg The amd gpu checks seem to be no-ops since it just stuffs the ID into s0, but that's the same as adding the ID to 0. For example,

s10 & 0x000000ff -> 0x0000000a
s0 -> 0x94010b00
s10 & 0x000000ff | s0 -> 0x94010b0a -> s10

Should it be mapping s<N> to s0?

I would think the AMD scalar and vector registers should be their own base register, so that is likely a bug unless @bbiiggppiigg says otherwise.

If we are talking about the implementation in MachRegister::getBaseRegister
I think this was related how multiregister was implemented in the old days.
Back then I defined each multiregister as a separate register whose base is the register with the lowest regID.
So something like SGPR_VEC4_0_3 (s[0:3]) should have a base s0.
As Jim said, each scalar register and vector register should be their own base register.
Right now it should be doing the right thing but just being redundant?

[kupsch]

In MachRegister.C, MachRegister::getBaseRegister, maps Sx to S0 and Vx to V0 for all values of x instead of mapping to the same register. The base register the largest containing physical register for the pseudoregister, such as x86's al mapping to rax.

[bbiiggppiigg]

In MachRegister.C, MachRegister::getBaseRegister, maps Sx to S0 and Vx to V0 for all values of x instead of mapping to the same register. The base register the largest containing physical register for the pseudoregister, such as x86's al mapping to rax.

I'm confused.
Are you saying the current implementation maps Sx to S0 and Vx to V0 for all values of x?
Or are you saying that it should?

If I look at the current implementation
https://github.com/dyninst/dyninst/blob/c1eafcd47f0f136951f6951a9e48655f48115617/common/src/registers/MachRegister.C#L142-L143
It seems to be doing what Tim described, doing no-ops.

[kupsch]

Never mind. The code is the identity function, but confusing. Here is the code:

          case amdgpu_gfx908::SGPR: return MachRegister((reg & 0x000000ff) | amdgpu_gfx908::s0);

It clears all but the lower byte of reg, and then ors the upper 3 bytes of s0 along with a zero for the lower byte. This results in the same value as reg. Why not MacRegister(reg)?

[hainest]

I've disabled running the amdgpu tests until we can decide on how best to represent their base registers.