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[as4224/as5114/as4564] Update DTS #154

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[as4224/as5114/as4564] Update DTS #154

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11 changes: 8 additions & 3 deletions packages/base/any/kernels/5.10-lts/patches/0012-accton-as4224.patch
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
diff --git a/arch/arm64/boot/dts/marvell/accton-as4224.dts b/arch/arm64/boot/dts/marvell/accton-as4224.dts
new file mode 100644
index 0000000..ee43c1e
index 0000000..e9234e1
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/accton-as4224.dts
@@ -0,0 +1,459 @@
@@ -0,0 +1,464 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
Expand Down Expand Up @@ -285,6 +285,7 @@ index 0000000..ee43c1e
+};
+
+&cp0_pcie0 {
+ dma-ranges = <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x40000000>;
+ ranges = <0x81000000 0x0 0xfb000000 0x0 0xfb000000 0x0 0xf0000
+ 0x82000000 0x0 0xf6000000 0x0 0xf6000000 0x0 0x2000000
+ 0x82000000 0x0 0xf9000000 0x0 0xf9000000 0x0 0x100000>;
Expand Down Expand Up @@ -393,13 +394,17 @@ index 0000000..ee43c1e
+ };
+};
+
+&cp0_comphy1 {
+ phy-skip-config;
+};
+
+&cp0_sata0 {
+ status = "okay";
+
+ sata-port@1 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy1 0>;
+ //phys = <&cp0_comphy1 0>;
+ };
+};
+
Expand Down
11 changes: 8 additions & 3 deletions packages/base/any/kernels/5.10-lts/patches/0020-accton-as5114.patch
View file
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
diff --git a/arch/arm64/boot/dts/marvell/accton-as5114.dts b/arch/arm64/boot/dts/marvell/accton-as5114.dts
new file mode 100644
index 0000000..68dc6b3
index 0000000..8351ec0
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/accton-as5114.dts
@@ -0,0 +1,1912 @@
@@ -0,0 +1,1917 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
Expand Down Expand Up @@ -1738,6 +1738,7 @@ index 0000000..68dc6b3
+};
+
+&cp0_pcie0 {
+ dma-ranges = <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x40000000>;
+ ranges = <0x81000000 0x0 0xfb000000 0x0 0xfb000000 0x0 0xf0000
+ 0x82000000 0x0 0xf6000000 0x0 0xf6000000 0x0 0x2000000
+ 0x82000000 0x0 0xf9000000 0x0 0xf9000000 0x0 0x100000>;
Expand Down Expand Up @@ -1846,13 +1847,17 @@ index 0000000..68dc6b3
+ };
+};
+
+&cp0_comphy1 {
+ phy-skip-config;
+};
+
+&cp0_sata0 {
+ status = "okay";
+
+ sata-port@1 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy1 0>;
+ //phys = <&cp0_comphy1 0>;
+ };
+};
+
Expand Down
11 changes: 8 additions & 3 deletions packages/base/any/kernels/5.10-lts/patches/0023-accton-as4564-26p.patch
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
diff --git a/arch/arm64/boot/dts/marvell/accton-as4564-26p.dts b/arch/arm64/boot/dts/marvell/accton-as4564-26p.dts
new file mode 100644
index 000000000..9852aa3b6
index 0000000..cee3779
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/accton-as4564-26p.dts
@@ -0,0 +1,394 @@
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
Expand Down Expand Up @@ -221,6 +221,7 @@ index 000000000..9852aa3b6
+};
+
+&cp0_pcie0 {
+ dma-ranges = <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x40000000>;
+ ranges = <0x81000000 0x0 0xfb000000 0x0 0xfb000000 0x0 0xf0000
+ 0x82000000 0x0 0xf6000000 0x0 0xf6000000 0x0 0x2000000
+ 0x82000000 0x0 0xf9000000 0x0 0xf9000000 0x0 0x100000>;
Expand Down Expand Up @@ -328,13 +329,17 @@ index 000000000..9852aa3b6
+ };
+};
+
+&cp0_comphy1 {
+ phy-skip-config;
+};
+
+&cp0_sata0 {
+ status = "okay";
+
+ sata-port@1 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy1 0>;
+ //phys = <&cp0_comphy1 0>;
+ };
+};
+
Expand Down