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@sequencer sequencer commented May 28, 2021

I'm currently working on cleaning chisel ir, I found it is strange to map both chisel3.internal.firrtl.DefRegInit and chisel3.internal.firrtl.DefReg to firrtl.ir.DefRegister. This PR corrects this.

Contributor Checklist

  • Did you add Scaladoc to every public function/method?
  • Did you add at least one test demonstrating the PR?
  • Did you delete any extraneous printlns/debugging code?
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Type of Improvement

  • code cleanup

API Impact

None

Backend Code Generation Impact

None

Desired Merge Strategy

f- Rebase: You will rebase the PR onto master and it will be merged with a merge commit.

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Reviewer Checklist (only modified by reviewer)

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  • Did you mark as Please Merge?

@sequencer sequencer requested a review from seldridge May 28, 2021 09:46
@sequencer sequencer force-pushed the ir_remove_reginit branch from 61b96c9 to 62d5220 Compare May 28, 2021 10:04
case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition
case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Option[Arg], init: Option[Arg]) extends Definition {
assert((reset.isDefined && init.isDefined) || (reset.isEmpty && init.isEmpty))
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what is the user experience if this fails? whats an example error message that they will get?

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User will never touch this code, since it's internal API. I'll add a error message if some-devs come into this.

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error message added in commit 919e965

@sequencer sequencer force-pushed the ir_remove_reginit branch from d398e9e to 919e965 Compare May 28, 2021 12:16
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This saves some line count by changing an internal API. That seems fine to me.

I'd prefer to use Option[(Arg, Arg)] to avoid the need for a possible assertion failure (which admittedly should never occur).

@sequencer sequencer force-pushed the ir_remove_reginit branch from 919e965 to 4a753f0 Compare June 2, 2021 05:47
@sequencer sequencer requested a review from jackkoenig June 2, 2021 05:47
@jackkoenig jackkoenig added this to the 3.5.0 milestone Jun 14, 2021
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If I recall correctly, there was some issue with either chiseltest or chisel-testers. Can you check if they both compile with this change @sequencer? And if not, please file corresponding PR(s) on the broken repo(s).

sequencer added a commit to sequencer/chisel-testers that referenced this pull request Jul 11, 2021
sequencer added a commit to ucb-bar/chiseltest that referenced this pull request Jul 11, 2021
@sequencer sequencer requested a review from jackkoenig August 8, 2021 15:52
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ask for review again by @jackkoenig

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Related chisel-testers PR: freechipsproject/chisel-testers#318
Related chiseltest PR: ucb-bar/chiseltest#332 (closed because the modified code was deleted)

@jackkoenig jackkoenig added the Please Merge Accepted PRs that are ready to be merged. Useful when waiting on CI. label Aug 17, 2021
@jackkoenig jackkoenig changed the title remove DefRegInit, change DefReg API with option defination. remove DefRegInit, change DefReg API with option definition. Aug 17, 2021
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5 participants