Skip to content

Conversation

@ThePassionate
Copy link
Contributor

TriCore CSRM: Bring-up CPUCS in TriCore

Summary

This PR adds support for bringing up the CPUCS (CPU Core Support) module in TriCore architecture with secure core (CSRM) functionality. It includes necessary initialization and configuration updates for proper TriCore secure core operations.

Changes

Files Modified

  1. arch/tricore/src/common/Ifx_Cfg_Trap.h

    • Add CPUCS trap configuration support for secure core operations
    • Enable proper trap handling for secure core CPUCS operations
  2. arch/tricore/src/common/tricore_main.c

    • Initialize core6_main() function for secure core
    • Add core_main() call for proper secure core initialization sequence

Technical Details

TriCore Secure Core Enhancement:

  • Enables CPUCS (CPU Core Support) bring-up in TriCore secure core (CSRM)
  • Provides necessary initialization for secure core (core6) execution
  • Maintains proper secure core initialization order and sequence

Trap Configuration:

  • Updates Ifx_Cfg_Trap.h with required CPUCS trap definitions for secure core
  • Ensures proper trap handling for TriCore secure core operations

Impact

  • Security Architecture: Enhances TriCore secure core (CSRM) support in NuttX
  • Secure Core: Enables proper initialization of secure core processors
  • CPUCS: Improves CPU Core Support functionality for secure core
  • Compatibility: Maintains backward compatibility with existing TriCore configurations

Testing

Test Environment:

  • TriCore architecture with secure core (CSRM)
  • NuttX standard build system

Test Procedure:

  1. Build NuttX with TriCore secure core architecture support
  2. Verify trap configuration loads correctly for secure core
  3. Validate core6_main() execution and initialization in secure core
  4. Confirm proper core_main() invocation in secure environment
  5. Test secure core functionality

Test Results:

  • ✅ Trap configuration applies successfully to secure core
  • ✅ Secure core (core6) initialization functions properly
  • ✅ Secure core main execution sequence is correct
  • ✅ No regressions in existing TriCore functionality
  • ✅ Secure core support operational

Related Issues

  • TriCore secure core (CSRM) bring-up support
  • CPUCS initialization and configuration for secure core
  • TriCore secure core architecture enhancement

@github-actions github-actions bot added Arch: tricore Issues related to the TriCore architecture from Infineon Size: XS The size of the change in this PR is very small labels Jan 16, 2026
Add CPUCS bring-up support for TriCore secure core (CSRM) module.
Enables core6 initialization for secure core operations.

Signed-off-by: makejian <makejian@xiaomi.com>
@github-actions github-actions bot added Area: Drivers Drivers issues Area: Crypto Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces. labels Jan 17, 2026
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

Arch: tricore Issues related to the TriCore architecture from Infineon Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces. Size: XS The size of the change in this PR is very small

Projects

None yet

Development

Successfully merging this pull request may close these issues.

2 participants