Fix CSEL/CSINC/CSINV/CSNEG treating r15 as PC instead of zero in Thumb legacy decoder#24
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…b legacy decoder Per the Armv8.1-M specification, register field 0b1111 in CSEL/CSINC/CSINV/CSNEG instructions encodes the zero register, not the program counter. The legacy Thumb-32 decoder in arch/arm/translate.c (used by 32-bit ARM targets like Cortex-M55) called load_reg() for these fields, which returns the PC value when the register is 15. This caused CSET (an alias for CSINC with both sources as ZR) to produce PC-derived values instead of the expected 0 or 1.
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Per the Armv8.1-M specification, register field 0b1111 in CSEL/CSINC/CSINV/CSNEG instructions encodes the zero register, not the program counter. The legacy Thumb-32 decoder in arch/arm/translate.c (used by 32-bit ARM targets like Cortex-M55) called load_reg() for these fields, which returns the PC value when the register is 15. This caused CSET (an alias for CSINC with both sources as ZR) to produce PC-derived values instead of the expected 0 or 1.